82 lines
3.2 KiB
C
82 lines
3.2 KiB
C
/* $NetBSD: fpu.h,v 1.1 2002/10/24 13:58:48 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Definitions for the SH5's Floating Point Unit
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*/
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#ifndef _SH5_FPU_H
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#define _SH5_FPU_H
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/*
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* Bits in the Floating Point Status and Control Register
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*/
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/* Rounding mode */
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#define SH5_FPSCR_RM_MASK 0x00001
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#define SH5_FPSCR_RM_TO_NEAREST 0x00000
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#define SH5_FPSCR_RM_TO_ZERO 0x00001
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/* Sticky Flags */
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#define SH5_FPSCR_FLAG_I 0x00004 /* Inexact */
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#define SH5_FPSCR_FLAG_U 0x00008 /* Underflow */
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#define SH5_FPSCR_FLAG_O 0x00010 /* Overflow */
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#define SH5_FPSCR_FLAG_Z 0x00020 /* Divide by Zero */
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#define SH5_FPSCR_FLAG_V 0x00040 /* Invalid */
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/* Enable Flags */
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#define SH5_FPSCR_ENABLE_I 0x00080 /* Inexact */
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#define SH5_FPSCR_ENABLE_U 0x00100 /* Underflow */
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#define SH5_FPSCR_ENABLE_O 0x00200 /* Overflow */
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#define SH5_FPSCR_ENABLE_Z 0x00400 /* Divide by Zero */
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#define SH5_FPSCR_ENABLE_V 0x00800 /* Invalid */
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/* Cause Flags */
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#define SH5_FPSCR_CAUSE_I 0x01000 /* Inexact */
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#define SH5_FPSCR_CAUSE_U 0x02000 /* Underflow */
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#define SH5_FPSCR_CAUSE_O 0x04000 /* Overflow */
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#define SH5_FPSCR_CAUSE_Z 0x08000 /* Divide by Zero */
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#define SH5_FPSCR_CAUSE_V 0x10000 /* Invalid */
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#define SH5_FPSCR_CAUSE_E 0x20000 /* FPU Error */
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/* Treatment of denormalised source operands */
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#define SH5_FPSCR_DN_MASK 0x40000
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#define SH5_FPSCR_DN_RAISE 0x00000 /* Raise an exception */
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#define SH5_FPSCR_DN_FLUSH_ZERO 0x40000 /* Flush to zero */
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#endif /* _SH5_FPU_H */
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