91 lines
3.8 KiB
C
91 lines
3.8 KiB
C
/* $NetBSD: tmureg.h,v 1.1 2002/07/05 13:31:55 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH5_TMUREG_H
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#define _SH5_TMUREG_H
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#define TMU_REG_TOCR 0x00 /* Timer output control register */
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#define TMU_REG_TSTR 0x04 /* Timer start register */
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#define TMU_REG_TCOR(t) (0x08+((t)*0x0c)) /* Timer constant registers */
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#define TMU_REG_TCNT(t) (0x0c+((t)*0x0c)) /* Timer counter registers */
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#define TMU_REG_TCR(t) (0x10+((t)*0x0c)) /* Timer control registers */
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#define TMU_REG_TCPR2 0x2c /* Input capture register */
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#define TMU_REG_SIZE 0x30
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#define TMU_NTIMERS 3
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/*
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* Bit definitions for TMU_REG_TOCR
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*/
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#define TMU_TOCR_TCOE 0x01 /* Timer output control */
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/*
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* Bit definitions for TMU_REG_TSTR
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*/
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#define TMU_TSTR(t) (1<<(t)) /* Counter `t' start */
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/*
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* Bit definitions for TMU_REG_TCR
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* (For all timers)
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*/
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#define TMU_TCR_TPSC_MASK 0x0007 /* Timer prescaler mask */
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#define TMU_TCR_TPSC_PDIV4 0 /* Peripheral clock / 4 */
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#define TMU_TCR_TPSC_PDIV16 1 /* Peripheral clock / 16 */
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#define TMU_TCR_TPSC_PDIV64 2 /* Peripheral clock / 64 */
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#define TMU_TCR_TPSC_PDIV256 3 /* Peripheral clock / 256 */
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#define TMU_TCR_TPSC_PDIV1024 4 /* Peripheral clock / 1024 */
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#define TMU_TCR_TPSC_RTC_OUT 6 /* On-chip RTC output clock */
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#define TMU_TCR_TPSC_EXT 7 /* External clock source */
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#define TMU_TCR_CKEG_MASK 0x0018 /* External clock edge select */
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#define TMU_TCR_CKEG_RISING 0x0000 /* Clock tick on rising edge */
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#define TMU_TCR_CKEG_FALLING 0x0008 /* Clock tick on falling edge */
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#define TMU_TCR_CKEG_BOTH 0x0010 /* Clock tick on both edges */
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#define TMU_TCR_UNIE 0x0020 /* Underflow interrupt enable */
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#define TMU_TCR_UNF 0x0100 /* Underflow occurred */
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/*
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* Additional bit definitions for TMU_REG_TCR
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* (For timer 2)
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*/
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#define TMU_TCR_ICPE_MASK 0x00c0 /* Input capture control */
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#define TMU_TCR_ICPE_OFF 0x0000 /* Input capture disabled */
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#define TMU_TCR_ICPE_ENOINT 0x0080 /* Input capture enabled, no irq */
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#define TMU_TCR_ICPE_EINT 0x00c0 /* Input capture enabled, irq enabled */
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#define TMU_TCR_ICPF 0x0100 /* Input capture occurred */
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#endif /* _SH5_TMUREG_H */
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