59 lines
2.7 KiB
C
59 lines
2.7 KiB
C
/*
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: dmavar.h,v 1.1 1994/09/17 23:48:35 deraadt Exp $
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*/
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struct dma_softc {
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struct device sc_dev; /* us as a device */
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struct sbusdev sc_sd; /* sbus device */
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struct esp_softc *sc_esp; /* my scsi */
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volatile u_long *sc_reg; /* the registers */
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int sc_active; /* DMA active ? */
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int sc_rev; /* revision */
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int sc_node; /* PROM node ID */
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size_t sc_dmasize;
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caddr_t *sc_dmaaddr;
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size_t *sc_dmalen;
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void (*reset)(struct dma_softc *); /* reset routine */
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void (*enintr)(struct dma_softc *); /* enable interrupts */
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void (*start)(struct dma_softc *, caddr_t *, size_t *, int);
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int (*isintr)(struct dma_softc *); /* intrerrupt ? */
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int (*intr)(struct dma_softc *); /* intrerrupt ! */
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};
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/*
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* We are not allowed to touch the DMA "flush" and "drain" bits
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* while it is still thinking about a request (DMA_RP).
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*/
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#define DMAWAIT(dma) while ((dma)[DMA_D_CSR] & D_R_PEND) DELAY(1)
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#define DMAWAIT1(dma) while ((dma)[DMA_D_CSR] & D_DRAINING) DELAY(1)
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#define DMAREADY(dma) while (!((dma)[DMA_D_CSR] & D_DMA_ON)) DELAY(1)
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#define DMACSR(r) r->sc_reg[DMA_D_CSR]
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#define DMADDR(r) r->sc_reg[DMA_D_ADDR]
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