138 lines
6.0 KiB
C
138 lines
6.0 KiB
C
/* $NetBSD: vaddrs.h,v 1.9 1998/08/23 09:53:03 pk Exp $ */
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/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard College. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* This product includes software developed by Harvard University.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)vaddrs.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Special (fixed) virtual addresses on the SPARC.
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*
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* IO virtual space begins at 0xfe000000 (a segment boundary) and
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* continues up to the DMVA edge at 0xff000000. (The upper all-1s
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* byte is special since some of the hardware supplies this to pad
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* a 24-bit address space out to 32 bits. This is a legacy of the
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* IBM PC AT bus, actually, just so you know who to blame.)
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*
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* We reserve several pages at the base of our IO virtual space
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* for `oft-used' devices which must be present anyway in order to
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* configure. In particular, we want the counter-timer register and
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* the Zilog ZSCC serial port chips to be mapped at fixed VAs to make
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* microtime() and the zs hardware interrupt handlers faster.
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*
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* [sun4/sun4c:]
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* Ideally, we should map the interrupt enable register here as well,
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* but that would require allocating pmegs in locore.s, so instead we
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* use one of the two `wasted' pages at KERNBASE+_MAXNBPG (see locore.s).
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*/
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#ifndef IODEV_0
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#define IODEV_0 0xfe000000 /* must match VM_MAX_KERNEL_ADDRESS */
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#define _MAXNBPG 8192 /* fixed VAs, independent of actual NBPG */
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#define _MAXNCPU 4 /* fixed VA allocation allows 4 CPUs */
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/* [4m:] interrupt and counter registers take (1 + NCPU) pages. */
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#define TIMERREG_VA (IODEV_0)
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#define COUNTERREG_VA ( TIMERREG_VA + _MAXNBPG*_MAXNCPU) /* [4m] */
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#define ZS0_VA (COUNTERREG_VA + _MAXNBPG)
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#define ZS1_VA ( ZS0_VA + _MAXNBPG)
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#define AUXREG_VA ( ZS1_VA + _MAXNBPG)
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#define TMPMAP_VA ( AUXREG_VA + _MAXNBPG)
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#define MSGBUF_VA ( TMPMAP_VA + _MAXNBPG)
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#define INTRREG_VA ( MSGBUF_VA + _MAXNBPG) /* [4/4c] */
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#define PI_INTR_VA ( MSGBUF_VA + _MAXNBPG) /* [4m] */
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#define SI_INTR_VA ( PI_INTR_VA + _MAXNBPG*_MAXNCPU) /* [4m] */
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#define IODEV_BASE ( SI_INTR_VA + _MAXNBPG)
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#define IODEV_END 0xff000000 /* 16 MB of iospace */
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/*
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* DVMA range for 24 bit devices.
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*/
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#define D24_DVMA_BASE 0xff000000
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#define D24_DVMA_END VME4_DVMA_BASE
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/*
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* DMA on sun4 VME devices use the last MB of virtual space, which
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* is mapped by hardware onto the first MB of VME space.
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* The DVMA area ends before the PROM mappings appear in the address space.
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*/
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#define VME4_DVMA_BASE 0xfff00000
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#define VME4_DVMA_END 0xfffc0000
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/*
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* The next constant defines the amount of reserved DVMA space on the
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* Sun4m. The amount of space *must* be a multiple of 16MB, and thus
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* (((u_int)0) - IOMMU_DVMA_BASE) must be divisible by 16*1024*1024!
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* Note that pagetables must be allocated at a cost of 1k per MB of DVMA
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* space, plus severe alignment restrictions. So don't make IOMMU_DVMA_BASE
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* too low (max space = 2G).
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*
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* Since DVMA space overlaps with normal kernel address space (notably
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* the device mappings and the PROM), we don't want to put any DVMA
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* mappings where any of this useful stuff is (i.e. if we dvma_malloc
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* a buffer, we want to still have a SRMMU mapping to it, and we can't
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* have that if its on top of kernel code). Thus the last two
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* constants define the actual DVMA addresses used. These can be anything
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* as long as they are within the bounds setup by the first 2 constants.
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* This is especially important on MP systems with cache coherency: to
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* avoid consistency problems, DVMA addresses must map to the same place
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* in both processor and IOMMU space.
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*/
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#define IOMMU_DVMA_BASE 0xfc000000 /* can change subject to above rule */
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#if 0
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#define IOMMU_DVMA_TOP 0xffffffff /* do not modify */
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#define IOMMU_DVMA_START 0xfd000000 /* 16M of DVMA */
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#endif
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#define IOMMU_DVMA_END 0xfe000000 /* XXX is this enough? */
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/*
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* Virtual address of the per cpu `cpu_softc' structure.
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*/
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#define CPUINFO_VA (KERNBASE+8192)
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#endif /* IODEV_0 */
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