1212 lines
28 KiB
C
1212 lines
28 KiB
C
/* $NetBSD: smc91cxx.c,v 1.17 1999/05/18 23:52:56 thorpej Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Gardner Buchanan.
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* 4. The name of Gardner Buchanan may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp
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*/
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/*
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* Core driver for the SMC 91Cxx family of Ethernet chips.
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*
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* Memory allocation interrupt logic is drived from an SMC 91C90 driver
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* written for NetBSD/amiga by Michael Hitch.
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*/
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#include "opt_inet.h"
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#include "opt_ccitt.h"
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#include "opt_llc.h"
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#include "opt_ns.h"
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#include "bpfilter.h"
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#include "rnd.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/syslog.h>
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#include <sys/socket.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#if NRND > 0
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#include <sys/rnd.h>
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#endif
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_ether.h>
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#include <net/if_media.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#include <netinet/in_systm.h>
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#include <netinet/in_var.h>
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#include <netinet/ip.h>
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#endif
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#ifdef NS
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#include <netns/ns.h>
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#include <netns/ns_if.h>
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#endif
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#if defined(CCITT) && defined(LLC)
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#include <sys/socketvar.h>
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#include <netccitt/x25.h>
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#include <netccitt/pk.h>
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#include <netccitt/pk_var.h>
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#include <netccitt/pk_extern.h>
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#endif
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#include <net/bpfdesc.h>
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#endif
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#include <dev/ic/smc91cxxreg.h>
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#include <dev/ic/smc91cxxvar.h>
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/* XXX Hardware padding doesn't work yet(?) */
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#define SMC91CXX_SW_PAD
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const char *smc91cxx_idstrs[] = {
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NULL, /* 0 */
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NULL, /* 1 */
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NULL, /* 2 */
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"SMC91C90/91C92", /* 3 */
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"SMC91C94", /* 4 */
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"SMC91C95", /* 5 */
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NULL, /* 6 */
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"SMC91C100", /* 7 */
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NULL, /* 8 */
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NULL, /* 9 */
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NULL, /* 10 */
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NULL, /* 11 */
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NULL, /* 12 */
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NULL, /* 13 */
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NULL, /* 14 */
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NULL, /* 15 */
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};
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/* Supported media types. */
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const int smc91cxx_media[] = {
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IFM_ETHER|IFM_10_T,
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IFM_ETHER|IFM_10_5,
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};
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#define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0]))
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int smc91cxx_mediachange __P((struct ifnet *));
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void smc91cxx_mediastatus __P((struct ifnet *, struct ifmediareq *));
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int smc91cxx_set_media __P((struct smc91cxx_softc *, int));
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void smc91cxx_init __P((struct smc91cxx_softc *));
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void smc91cxx_read __P((struct smc91cxx_softc *));
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void smc91cxx_reset __P((struct smc91cxx_softc *));
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void smc91cxx_start __P((struct ifnet *));
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void smc91cxx_resume __P((struct smc91cxx_softc *));
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void smc91cxx_stop __P((struct smc91cxx_softc *));
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void smc91cxx_watchdog __P((struct ifnet *));
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int smc91cxx_ioctl __P((struct ifnet *, u_long, caddr_t));
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static __inline int ether_cmp __P((void *, void *));
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static __inline int
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ether_cmp(va, vb)
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void *va, *vb;
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{
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u_int8_t *a = va;
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u_int8_t *b = vb;
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return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) ||
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(a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0]));
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}
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void
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smc91cxx_attach(sc, myea)
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struct smc91cxx_softc *sc;
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u_int8_t *myea;
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{
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struct ifnet *ifp = &sc->sc_ec.ec_if;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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const char *idstr;
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u_int16_t tmp;
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u_int8_t enaddr[ETHER_ADDR_LEN];
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int i, aui;
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/* Make sure the chip is stopped. */
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smc91cxx_stop(sc);
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SMC_SELECT_BANK(sc, 3);
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tmp = bus_space_read_2(bst, bsh, REVISION_REG_W);
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idstr = smc91cxx_idstrs[RR_ID(tmp)];
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printf("%s: ", sc->sc_dev.dv_xname);
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if (idstr != NULL)
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printf("%s, ", idstr);
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else
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printf("unknown chip id %d, ", RR_ID(tmp));
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printf("revision %d\n", RR_REV(tmp));
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/* Read the station address from the chip. */
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SMC_SELECT_BANK(sc, 1);
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if (myea == NULL) {
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myea = enaddr;
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for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
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tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i);
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myea[i + 1] = (tmp >> 8) & 0xff;
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myea[i] = tmp & 0xff;
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}
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}
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printf("%s: MAC address %s, ", sc->sc_dev.dv_xname,
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ether_sprintf(myea));
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/* ..and default media. */
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tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
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printf("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ?
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"AUI" : "UTP");
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/* Initialize the ifnet structure. */
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bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
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ifp->if_softc = sc;
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ifp->if_start = smc91cxx_start;
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ifp->if_ioctl = smc91cxx_ioctl;
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ifp->if_watchdog = smc91cxx_watchdog;
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ifp->if_flags =
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IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
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/* Attach the interface. */
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if_attach(ifp);
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ether_ifattach(ifp, myea);
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/* Initialize the media structures. */
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ifmedia_init(&sc->sc_media, 0, smc91cxx_mediachange,
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smc91cxx_mediastatus);
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for (i = 0; i < NSMC91CxxMEDIA; i++)
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ifmedia_add(&sc->sc_media, smc91cxx_media[i], 0, NULL);
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ifmedia_set(&sc->sc_media, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T));
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#if NBPFILTER > 0
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bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
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#endif
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#if NRND > 0
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rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
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RND_TYPE_NET, 0);
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#endif
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}
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/*
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* Change media according to request.
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*/
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int
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smc91cxx_mediachange(ifp)
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struct ifnet *ifp;
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{
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struct smc91cxx_softc *sc = ifp->if_softc;
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return (smc91cxx_set_media(sc, sc->sc_media.ifm_media));
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}
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int
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smc91cxx_set_media(sc, media)
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struct smc91cxx_softc *sc;
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int media;
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{
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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u_int16_t tmp;
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/*
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* If the interface is not currently powered on, just return.
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* When it is enabled later, smc91cxx_init() will properly set
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* up the media for us.
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*/
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if (sc->sc_enabled == 0)
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return (0);
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if (IFM_TYPE(media) != IFM_ETHER)
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return (EINVAL);
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switch (IFM_SUBTYPE(media)) {
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case IFM_10_T:
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case IFM_10_5:
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SMC_SELECT_BANK(sc, 1);
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tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
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if (IFM_SUBTYPE(media) == IFM_10_5)
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tmp |= CR_AUI_SELECT;
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else
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tmp &= ~CR_AUI_SELECT;
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bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp);
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delay(20000); /* XXX is this needed? */
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break;
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default:
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return (EINVAL);
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}
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return (0);
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}
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/*
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* Notify the world which media we're using.
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*/
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void
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smc91cxx_mediastatus(ifp, ifmr)
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struct ifnet *ifp;
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struct ifmediareq *ifmr;
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{
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struct smc91cxx_softc *sc = ifp->if_softc;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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u_int16_t tmp;
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if (sc->sc_enabled == 0) {
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ifmr->ifm_active = IFM_ETHER | IFM_NONE;
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ifmr->ifm_status = 0;
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return;
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}
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SMC_SELECT_BANK(sc, 1);
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tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
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ifmr->ifm_active =
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IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T);
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}
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/*
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* Reset and initialize the chip.
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*/
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void
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smc91cxx_init(sc)
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struct smc91cxx_softc *sc;
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{
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struct ifnet *ifp = &sc->sc_ec.ec_if;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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u_int16_t tmp;
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u_int8_t *enaddr;
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int s, i;
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s = splnet();
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/*
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* This resets the registersmostly to defaults, but doesn't
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* affect the EEPROM. After the reset cycle, we pause briefly
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* for the chip to recover.
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*
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* XXX how long are we really supposed to delay? --thorpej
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*/
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SMC_SELECT_BANK(sc, 0);
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bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET);
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delay(100);
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bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0);
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delay(200);
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bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0);
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/* Set the Ethernet address. */
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SMC_SELECT_BANK(sc, 1);
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enaddr = (u_int8_t *)LLADDR(ifp->if_sadl);
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for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
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tmp = enaddr[i + 1] << 8 | enaddr[i];
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bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp);
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}
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/*
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* Set the control register to automatically release successfully
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* transmitted packets (making the best use of our limited memory)
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* and enable the EPH interrupt on certain TX errors.
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*/
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bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE |
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CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE));
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/*
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* Reset the MMU and wait for it to be un-busy.
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*/
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SMC_SELECT_BANK(sc, 2);
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bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET);
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while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
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/* XXX bound this loop! */ ;
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/*
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* Disable all interrupts.
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*/
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bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0);
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/*
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* Set current media.
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*/
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smc91cxx_set_media(sc, sc->sc_media.ifm_cur->ifm_media);
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/*
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* Set the receive filter. We want receive enable and auto
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* strip of CRC from received packet. If we are in promisc. mode,
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* then set that bit as well.
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*
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* XXX Initialize multicast filter. For now, we just accept
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* XXX all multicast.
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*/
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SMC_SELECT_BANK(sc, 0);
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tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL;
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if (ifp->if_flags & IFF_PROMISC)
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tmp |= RCR_PROMISC;
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bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp);
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/*
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* Set transmitter control to "enabled".
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*/
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tmp = TCR_ENABLE;
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#ifndef SMC91CXX_SW_PAD
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/*
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* Enable hardware padding of transmitted packets.
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* XXX doesn't work?
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*/
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tmp |= TCR_PAD_ENABLE;
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#endif
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bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp);
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/*
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* Now, enable interrupts.
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*/
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SMC_SELECT_BANK(sc, 2);
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bus_space_write_1(bst, bsh, INTR_MASK_REG_B,
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IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT);
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/* Interface is now running, with no output active. */
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ifp->if_flags |= IFF_RUNNING;
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ifp->if_flags &= ~IFF_OACTIVE;
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/*
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* Attempt to start any pending transmission.
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*/
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smc91cxx_start(ifp);
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splx(s);
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}
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/*
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* Start output on an interface.
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* Must be called at splnet or interrupt level.
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*/
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void
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smc91cxx_start(ifp)
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struct ifnet *ifp;
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{
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struct smc91cxx_softc *sc = ifp->if_softc;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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u_int len;
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struct mbuf *m, *top;
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u_int16_t length, npages;
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u_int8_t packetno;
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int timo, pad;
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if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
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return;
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again:
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/*
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* Peek at the next packet.
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*/
|
|
if ((m = ifp->if_snd.ifq_head) == NULL)
|
|
return;
|
|
|
|
/*
|
|
* Compute the frame length and set pad to give an overall even
|
|
* number of bytes. Below, we assume that the packet length
|
|
* is even.
|
|
*/
|
|
for (len = 0, top = m; m != NULL; m = m->m_next)
|
|
len += m->m_len;
|
|
pad = (len & 1);
|
|
|
|
/*
|
|
* We drop packets that are too large. Perhaps we should
|
|
* truncate them instead?
|
|
*/
|
|
if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) {
|
|
printf("%s: large packet discarded\n", sc->sc_dev.dv_xname);
|
|
ifp->if_oerrors++;
|
|
IF_DEQUEUE(&ifp->if_snd, m);
|
|
m_freem(m);
|
|
goto readcheck;
|
|
}
|
|
|
|
#ifdef SMC91CXX_SW_PAD
|
|
/*
|
|
* Not using hardware padding; pad to ETHER_MIN_LEN.
|
|
*/
|
|
if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN))
|
|
pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
|
|
#endif
|
|
|
|
length = pad + len;
|
|
|
|
/*
|
|
* The MMU has a 256 byte page size. The MMU expects us to
|
|
* ask for "npages - 1". We include space for the status word,
|
|
* byte count, and control bytes in the allocation request.
|
|
*/
|
|
npages = (length + 6) >> 8;
|
|
|
|
/*
|
|
* Now allocate the memory.
|
|
*/
|
|
SMC_SELECT_BANK(sc, 2);
|
|
bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages);
|
|
|
|
timo = MEMORY_WAIT_TIME;
|
|
do {
|
|
if (bus_space_read_1(bst, bsh, INTR_STAT_REG_B) & IM_ALLOC_INT)
|
|
break;
|
|
delay(1);
|
|
} while (--timo);
|
|
|
|
packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B);
|
|
|
|
if (packetno & ARR_FAILED || timo == 0) {
|
|
/*
|
|
* No transmit memory is available. Record the number
|
|
* of requestd pages and enable the allocation completion
|
|
* interrupt. Set up the watchdog timer in case we miss
|
|
* the interrupt. Mark the interface as active so that
|
|
* no one else attempts to transmit while we're allocating
|
|
* memory.
|
|
*/
|
|
bus_space_write_1(bst, bsh, INTR_MASK_REG_B,
|
|
bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | IM_ALLOC_INT);
|
|
|
|
ifp->if_timer = 5;
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* We have a packet number - set the data window.
|
|
*/
|
|
bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno);
|
|
|
|
/*
|
|
* Point to the beginning of the packet.
|
|
*/
|
|
bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */);
|
|
|
|
/*
|
|
* Send the packet length (+6 for stats, length, and control bytes)
|
|
* and the status word (set to zeros).
|
|
*/
|
|
bus_space_write_2(bst, bsh, DATA_REG_W, 0);
|
|
bus_space_write_1(bst, bsh, DATA_REG_B, (length + 6) & 0xff);
|
|
bus_space_write_1(bst, bsh, DATA_REG_B, ((length + 6) >> 8) & 0xff);
|
|
|
|
/*
|
|
* Get the packet from the kernel. This will include the Ethernet
|
|
* frame header, MAC address, etc.
|
|
*/
|
|
IF_DEQUEUE(&ifp->if_snd, m);
|
|
|
|
/*
|
|
* Push the packet out to the card.
|
|
*/
|
|
for (top = m; m != NULL; m = m->m_next) {
|
|
/* Words... */
|
|
bus_space_write_multi_2(bst, bsh, DATA_REG_W,
|
|
mtod(m, u_int16_t *), m->m_len >> 1);
|
|
|
|
/* ...and the remaining byte, if any. */
|
|
if (m->m_len & 1)
|
|
bus_space_write_1(bst, bsh, DATA_REG_B,
|
|
*(u_int8_t *)(mtod(m, u_int8_t *) + (m->m_len - 1)));
|
|
}
|
|
|
|
#ifdef SMC91CXX_SW_PAD
|
|
/*
|
|
* Push out padding.
|
|
*/
|
|
while (pad > 1) {
|
|
bus_space_write_2(bst, bsh, DATA_REG_W, 0);
|
|
pad -= 2;
|
|
}
|
|
if (pad)
|
|
bus_space_write_1(bst, bsh, DATA_REG_B, 0);
|
|
#endif
|
|
|
|
/*
|
|
* Push out control byte and unused packet byte. The control byte
|
|
* is 0, meaning the packet is even lengthed and no special
|
|
* CRC handling is necessary.
|
|
*/
|
|
bus_space_write_2(bst, bsh, DATA_REG_W, 0);
|
|
|
|
/*
|
|
* Enable transmit interrupts and let the chip go. Set a watchdog
|
|
* in case we miss the interrupt.
|
|
*/
|
|
bus_space_write_1(bst, bsh, INTR_MASK_REG_B,
|
|
bus_space_read_1(bst, bsh, INTR_MASK_REG_B) |
|
|
IM_TX_INT | IM_TX_EMPTY_INT);
|
|
|
|
bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE);
|
|
|
|
ifp->if_timer = 5;
|
|
|
|
#if NBPFILTER > 0
|
|
/* Hand off a copy to the bpf. */
|
|
if (ifp->if_bpf)
|
|
bpf_mtap(ifp->if_bpf, top);
|
|
#endif
|
|
|
|
ifp->if_opackets++;
|
|
m_freem(top);
|
|
|
|
readcheck:
|
|
/*
|
|
* Check for incoming pcakets. We don't want to overflow the small
|
|
* RX FIFO. If nothing has arrived, attempt to queue another
|
|
* transmit packet.
|
|
*/
|
|
if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY)
|
|
goto again;
|
|
}
|
|
|
|
/*
|
|
* Interrupt service routine.
|
|
*/
|
|
int
|
|
smc91cxx_intr(arg)
|
|
void *arg;
|
|
{
|
|
struct smc91cxx_softc *sc = arg;
|
|
struct ifnet *ifp = &sc->sc_ec.ec_if;
|
|
bus_space_tag_t bst = sc->sc_bst;
|
|
bus_space_handle_t bsh = sc->sc_bsh;
|
|
u_int8_t mask, interrupts, status;
|
|
u_int16_t packetno, tx_status, card_stats;
|
|
|
|
if (sc->sc_enabled == 0)
|
|
return (0);
|
|
|
|
SMC_SELECT_BANK(sc, 2);
|
|
|
|
/*
|
|
* Obtain the current interrupt mask.
|
|
*/
|
|
mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B);
|
|
|
|
/*
|
|
* Get the set of interrupt which occurred and eliminate any
|
|
* which are not enabled.
|
|
*/
|
|
interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B);
|
|
status = interrupts & mask;
|
|
|
|
/* Ours? */
|
|
if (status == 0)
|
|
return (0);
|
|
|
|
/*
|
|
* It's ours; disable all interrupts while we process them.
|
|
*/
|
|
bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0);
|
|
|
|
/*
|
|
* Receive overrun interrupts.
|
|
*/
|
|
if (status & IM_RX_OVRN_INT) {
|
|
bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_RX_OVRN_INT);
|
|
ifp->if_ierrors++;
|
|
}
|
|
|
|
/*
|
|
* Receive interrupts.
|
|
*/
|
|
if (status & IM_RCV_INT) {
|
|
#if 1 /* DIAGNOSTIC */
|
|
packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W);
|
|
if (packetno & FIFO_REMPTY)
|
|
printf("%s: receive interrupt on empty fifo\n",
|
|
sc->sc_dev.dv_xname);
|
|
else
|
|
#endif
|
|
smc91cxx_read(sc);
|
|
}
|
|
|
|
/*
|
|
* Memory allocation interrupts.
|
|
*/
|
|
if (status & IM_ALLOC_INT) {
|
|
/* Disable this interrupt. */
|
|
mask &= ~IM_ALLOC_INT;
|
|
|
|
/*
|
|
* Release the just-allocated memory. We will reallocate
|
|
* it through the normal start logic.
|
|
*/
|
|
while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
|
|
/* XXX bound this loop! */ ;
|
|
bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT);
|
|
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
ifp->if_timer = 0;
|
|
}
|
|
|
|
/*
|
|
* Transmit complete interrupt. Handle transmission error messages.
|
|
* This will only be called on error condition because of AUTO RELEASE
|
|
* mode.
|
|
*/
|
|
if (status & IM_TX_INT) {
|
|
bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_INT);
|
|
|
|
packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) &
|
|
FIFO_TX_MASK;
|
|
|
|
/*
|
|
* Select this as the packet to read from.
|
|
*/
|
|
bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno);
|
|
|
|
/*
|
|
* Position the pointer to the beginning of the packet.
|
|
*/
|
|
bus_space_write_2(bst, bsh, POINTER_REG_W,
|
|
PTR_AUTOINC | PTR_READ /* | 0x0000 */);
|
|
|
|
/*
|
|
* Fetch the TX status word. This will be a copy of
|
|
* the EPH_STATUS_REG_W at the time of the transmission
|
|
* failure.
|
|
*/
|
|
tx_status = bus_space_read_2(bst, bsh, DATA_REG_W);
|
|
|
|
if (tx_status & EPHSR_TX_SUC)
|
|
printf("%s: successful packet caused TX interrupt?!\n",
|
|
sc->sc_dev.dv_xname);
|
|
else
|
|
ifp->if_oerrors++;
|
|
|
|
if (tx_status & EPHSR_LATCOL)
|
|
ifp->if_collisions++;
|
|
|
|
/*
|
|
* Some of these errors disable the transmitter; reenable it.
|
|
*/
|
|
SMC_SELECT_BANK(sc, 0);
|
|
#ifdef SMC91CXX_SW_PAD
|
|
bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE);
|
|
#else
|
|
bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W,
|
|
TCR_ENABLE | TCR_PAD_ENABLE);
|
|
#endif
|
|
|
|
/*
|
|
* Kill the failed packet and wait for the MMU to unbusy.
|
|
*/
|
|
SMC_SELECT_BANK(sc, 2);
|
|
while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
|
|
/* XXX bound this loop! */ ;
|
|
bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT);
|
|
|
|
ifp->if_timer = 0;
|
|
}
|
|
|
|
/*
|
|
* Transmit underrun interrupts. We use this opportunity to
|
|
* update transmit statistics from the card.
|
|
*/
|
|
if (status & IM_TX_EMPTY_INT) {
|
|
bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
|
|
|
|
/* Disable this interrupt. */
|
|
mask &= ~IM_TX_EMPTY_INT;
|
|
|
|
SMC_SELECT_BANK(sc, 0);
|
|
card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W);
|
|
|
|
/* Single collisions. */
|
|
ifp->if_collisions += card_stats & ECR_COLN_MASK;
|
|
|
|
/* Multiple collisions. */
|
|
ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
|
|
|
|
SMC_SELECT_BANK(sc, 2);
|
|
|
|
ifp->if_timer = 0;
|
|
}
|
|
|
|
/*
|
|
* Other errors. Reset the interface.
|
|
*/
|
|
if (status & IM_EPH_INT) {
|
|
smc91cxx_stop(sc);
|
|
smc91cxx_init(sc);
|
|
}
|
|
|
|
/*
|
|
* Attempt to queue more packets for transmission.
|
|
*/
|
|
smc91cxx_start(ifp);
|
|
|
|
/*
|
|
* Reenable the interrupts we wish to receive now that processing
|
|
* is complete.
|
|
*/
|
|
mask |= bus_space_read_1(bst, bsh, INTR_MASK_REG_B);
|
|
bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask);
|
|
|
|
#if NRND > 0
|
|
if (status)
|
|
rnd_add_uint32(&sc->rnd_source, status);
|
|
#endif
|
|
|
|
return (1);
|
|
}
|
|
|
|
/*
|
|
* Read a packet from the card and pass it up to the kernel.
|
|
* NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2!
|
|
*/
|
|
void
|
|
smc91cxx_read(sc)
|
|
struct smc91cxx_softc *sc;
|
|
{
|
|
struct ifnet *ifp = &sc->sc_ec.ec_if;
|
|
bus_space_tag_t bst = sc->sc_bst;
|
|
bus_space_handle_t bsh = sc->sc_bsh;
|
|
struct ether_header *eh;
|
|
struct mbuf *m;
|
|
u_int16_t status, packetno, packetlen;
|
|
u_int8_t *data;
|
|
|
|
again:
|
|
/*
|
|
* Set data pointer to the beginning of the packet. Since
|
|
* PTR_RCV is set, the packet number will be found automatically
|
|
* in FIFO_PORTS_REG_W, FIFO_RX_MASK.
|
|
*/
|
|
bus_space_write_2(bst, bsh, POINTER_REG_W,
|
|
PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */);
|
|
|
|
/*
|
|
* First two words are status and packet length.
|
|
*/
|
|
status = bus_space_read_2(bst, bsh, DATA_REG_W);
|
|
packetlen = bus_space_read_2(bst, bsh, DATA_REG_W);
|
|
|
|
/*
|
|
* The packet length includes 3 extra words: status, length,
|
|
* and an extra word that includes the control byte.
|
|
*/
|
|
packetlen -= 6;
|
|
|
|
/*
|
|
* Account for receive errors and discard.
|
|
*/
|
|
if (status & RS_ERRORS) {
|
|
ifp->if_ierrors++;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Adjust for odd-length packet.
|
|
*/
|
|
if (status & RS_ODDFRAME)
|
|
packetlen++;
|
|
|
|
/*
|
|
* Allocate a header mbuf.
|
|
*/
|
|
MGETHDR(m, M_DONTWAIT, MT_DATA);
|
|
if (m == NULL)
|
|
goto out;
|
|
|
|
m->m_pkthdr.rcvif = ifp;
|
|
m->m_pkthdr.len = m->m_len = packetlen;
|
|
|
|
/*
|
|
* Always put the packet in a cluster.
|
|
* XXX should chain small mbufs if less than threshold.
|
|
*/
|
|
MCLGET(m, M_DONTWAIT);
|
|
if ((m->m_flags & M_EXT) == 0) {
|
|
m_freem(m);
|
|
ifp->if_ierrors++;
|
|
printf("%s: can't allocate cluster for incoming packet\n",
|
|
sc->sc_dev.dv_xname);
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Pull the packet off the interface.
|
|
*/
|
|
eh = mtod(m, struct ether_header *);
|
|
data = mtod(m, u_int8_t *);
|
|
bus_space_read_multi_2(bst, bsh, DATA_REG_W, (u_int16_t *)data,
|
|
packetlen >> 1);
|
|
if (packetlen & 1) {
|
|
data += packetlen & ~1;
|
|
*data = bus_space_read_1(bst, bsh, DATA_REG_B);
|
|
}
|
|
|
|
ifp->if_ipackets++;
|
|
|
|
#if NBPFILTER > 0
|
|
/*
|
|
* Hand the packet off to bpf listeners. If there's a bpf listener,
|
|
* we need to check if the packet is ours.
|
|
*/
|
|
if (ifp->if_bpf) {
|
|
bpf_mtap(ifp->if_bpf, m);
|
|
|
|
if ((ifp->if_flags & IFF_PROMISC) &&
|
|
(eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */
|
|
ether_cmp(eh->ether_dhost, LLADDR(ifp->if_sadl))) {
|
|
m_freem(m);
|
|
goto out;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
m->m_pkthdr.len = m->m_len = packetlen;
|
|
(*ifp->if_input)(ifp, m);
|
|
|
|
out:
|
|
/*
|
|
* Tell the card to free the memory occupied by this packet.
|
|
*/
|
|
while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
|
|
/* XXX bound this loop! */ ;
|
|
bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE);
|
|
|
|
/*
|
|
* Check for another packet.
|
|
*/
|
|
packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W);
|
|
if (packetno & FIFO_REMPTY)
|
|
return;
|
|
goto again;
|
|
}
|
|
|
|
/*
|
|
* Process an ioctl request.
|
|
*/
|
|
int
|
|
smc91cxx_ioctl(ifp, cmd, data)
|
|
struct ifnet *ifp;
|
|
u_long cmd;
|
|
caddr_t data;
|
|
{
|
|
struct smc91cxx_softc *sc = ifp->if_softc;
|
|
struct ifaddr *ifa = (struct ifaddr *)data;
|
|
struct ifreq *ifr = (struct ifreq *)data;
|
|
int s, error = 0;
|
|
|
|
s = splnet();
|
|
|
|
switch (cmd) {
|
|
case SIOCSIFADDR:
|
|
if ((error = smc91cxx_enable(sc)) != 0)
|
|
break;
|
|
ifp->if_flags |= IFF_UP;
|
|
switch (ifa->ifa_addr->sa_family) {
|
|
#ifdef INET
|
|
case AF_INET:
|
|
smc91cxx_init(sc);
|
|
arp_ifinit(ifp, ifa);
|
|
break;
|
|
#endif
|
|
#ifdef NS
|
|
case AF_NS:
|
|
{
|
|
struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
|
|
|
|
if (ns_nullhost(*ina))
|
|
ina->x_host =
|
|
*(union ns_host *)LLADDR(ifp->if_sadl);
|
|
else {
|
|
bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl),
|
|
ETHER_ADDR_LEN);
|
|
}
|
|
|
|
/*
|
|
* Set new address. Reset, because the receiver
|
|
* has to be stopped before we can set the new
|
|
* MAC address.
|
|
*/
|
|
smc91cxx_reset(sc);
|
|
break;
|
|
}
|
|
#endif
|
|
default:
|
|
smc91cxx_init(sc);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
#if defined(CCITT) && defined(LLC)
|
|
case SIOCSIFCONF_X25:
|
|
if ((error = smc91cxx_enable(sc)) != 0)
|
|
break;
|
|
ifp->if_flags |= IFF_UP;
|
|
ifa->ifa_rtrequest = cons_rtrequest; /* XXX */
|
|
error = x25_llcglue(PRC_IFUP, ifa->ifa_addr);
|
|
if (error == 0)
|
|
smc91cxx_init(sc);
|
|
break;
|
|
#endif
|
|
|
|
case SIOCSIFFLAGS:
|
|
if ((ifp->if_flags & IFF_UP) == 0 &&
|
|
(ifp->if_flags & IFF_RUNNING) != 0) {
|
|
/*
|
|
* If interface is marked down and it is running,
|
|
* stop it.
|
|
*/
|
|
smc91cxx_stop(sc);
|
|
ifp->if_flags &= ~IFF_RUNNING;
|
|
smc91cxx_disable(sc);
|
|
} else if ((ifp->if_flags & IFF_UP) != 0 &&
|
|
(ifp->if_flags & IFF_RUNNING) == 0) {
|
|
/*
|
|
* If interface is marked up and it is stopped,
|
|
* start it.
|
|
*/
|
|
if ((error = smc91cxx_enable(sc)) != 0)
|
|
break;
|
|
smc91cxx_init(sc);
|
|
} else if ((ifp->if_flags & IFF_UP) != 0) {
|
|
/*
|
|
* Reset the interface to pick up changes in any
|
|
* other flags that affect hardware registers.
|
|
*/
|
|
smc91cxx_reset(sc);
|
|
}
|
|
break;
|
|
|
|
case SIOCADDMULTI:
|
|
case SIOCDELMULTI:
|
|
if (sc->sc_enabled == 0) {
|
|
error = EIO;
|
|
break;
|
|
}
|
|
|
|
error = (cmd == SIOCADDMULTI) ?
|
|
ether_addmulti(ifr, &sc->sc_ec) :
|
|
ether_delmulti(ifr, &sc->sc_ec);
|
|
if (error == ENETRESET) {
|
|
/*
|
|
* Multicast list has changed; set the hardware
|
|
* filter accordingly.
|
|
*/
|
|
smc91cxx_reset(sc);
|
|
error = 0;
|
|
}
|
|
break;
|
|
|
|
case SIOCGIFMEDIA:
|
|
case SIOCSIFMEDIA:
|
|
error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
|
|
break;
|
|
|
|
default:
|
|
error = EINVAL;
|
|
break;
|
|
}
|
|
|
|
splx(s);
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* Reset the interface.
|
|
*/
|
|
void
|
|
smc91cxx_reset(sc)
|
|
struct smc91cxx_softc *sc;
|
|
{
|
|
int s;
|
|
|
|
s = splnet();
|
|
smc91cxx_stop(sc);
|
|
smc91cxx_init(sc);
|
|
splx(s);
|
|
}
|
|
|
|
/*
|
|
* Watchdog timer.
|
|
*/
|
|
void
|
|
smc91cxx_watchdog(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct smc91cxx_softc *sc = ifp->if_softc;
|
|
|
|
log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
|
|
ifp->if_oerrors++;
|
|
smc91cxx_reset(sc);
|
|
}
|
|
|
|
/*
|
|
* Stop output on the interface.
|
|
*/
|
|
void
|
|
smc91cxx_stop(sc)
|
|
struct smc91cxx_softc *sc;
|
|
{
|
|
bus_space_tag_t bst = sc->sc_bst;
|
|
bus_space_handle_t bsh = sc->sc_bsh;
|
|
|
|
/*
|
|
* Clear interrupt mask; disable all interrupts.
|
|
*/
|
|
SMC_SELECT_BANK(sc, 2);
|
|
bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0);
|
|
|
|
/*
|
|
* Disable transmitter and receiver.
|
|
*/
|
|
SMC_SELECT_BANK(sc, 0);
|
|
bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0);
|
|
bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0);
|
|
|
|
/*
|
|
* Cancel watchdog timer.
|
|
*/
|
|
sc->sc_ec.ec_if.if_timer = 0;
|
|
}
|
|
|
|
/*
|
|
* Enable power on the interface.
|
|
*/
|
|
int
|
|
smc91cxx_enable(sc)
|
|
struct smc91cxx_softc *sc;
|
|
{
|
|
|
|
if (sc->sc_enabled == 0 && sc->sc_enable != NULL) {
|
|
if ((*sc->sc_enable)(sc) != 0) {
|
|
printf("%s: device enable failed\n",
|
|
sc->sc_dev.dv_xname);
|
|
return (EIO);
|
|
}
|
|
}
|
|
|
|
sc->sc_enabled = 1;
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Disable power on the interface.
|
|
*/
|
|
void
|
|
smc91cxx_disable(sc)
|
|
struct smc91cxx_softc *sc;
|
|
{
|
|
|
|
if (sc->sc_enabled != 0 && sc->sc_disable != NULL) {
|
|
(*sc->sc_disable)(sc);
|
|
sc->sc_enabled = 0;
|
|
}
|
|
}
|
|
|
|
int
|
|
smc91cxx_activate(self, act)
|
|
struct device *self;
|
|
enum devact act;
|
|
{
|
|
struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self;
|
|
int rv = 0, s;
|
|
|
|
s = splnet();
|
|
switch (act) {
|
|
case DVACT_ACTIVATE:
|
|
rv = EOPNOTSUPP;
|
|
break;
|
|
|
|
case DVACT_DEACTIVATE:
|
|
#ifdef notyet
|
|
/* First, kill off the interface. */
|
|
if_detach(sc->sc_ec.ec_if);
|
|
#endif
|
|
|
|
/* Now disable the interface. */
|
|
smc91cxx_disable(sc);
|
|
break;
|
|
}
|
|
splx(s);
|
|
return (rv);
|
|
}
|