107 lines
2.9 KiB
Groff
107 lines
2.9 KiB
Groff
.\" $NetBSD: gpiopps.4,v 1.2 2018/05/20 15:28:27 wiz Exp $
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.\"
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.\" Copyright (c) 2016 Brad Spencer <brad@anduin.eldar.org>
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.\"
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.\" Permission to use, copy, modify, and distribute this software for any
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.\" purpose with or without fee is hereby granted, provided that the above
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.\" copyright notice and this permission notice appear in all copies.
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.\"
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.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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.\"
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.Dd May 11, 2018
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.Dt GPIOPPS 4
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.Os
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.Sh NAME
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.Nm gpiopps
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.Nd install a PPS handler on GPIO pins
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.Sh SYNOPSIS
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.Cd "gpiopps* at gpio? offset 0 mask 0x1 flag 0x0"
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.Sh DESCRIPTION
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The
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.Nm
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driver provides a 1PPS handler using the PPSAPI on one or two GPIO pins.
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.Pp
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The base pin number is specified in the kernel configuration file with the
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.Ar offset
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locator.
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The
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.Ar mask
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should have 1 or 2 bits set, indicating which pins offset from the
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base pin should be used
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.Pq 0 .. 31 .
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Pin configurations are discussed below.
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.Pp
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The
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.Ar flag
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locator modifies the pin configuraiton:
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.Bl -tag -width "XXXXXXXX"
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.It Dv 0x01
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The PPS ASSERT signal should be triggered on the negative
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.Pq falling
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edge of the
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assert pin.
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The default is to trigger on the positive
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.Pq rising
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edge of the pin.
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.It Dv 0x02
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By default,
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.Nm
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will use double-edge triggering when only a single pin is specified
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and the underlying GPIO hardware supports it.
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This flag disables the use of double-edge triggering.
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.El
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.Pp
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If a single pin is specified,
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.Nm
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uses double-edge triggering to support ASSERT and CLEAR PPS signals.
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If the underlying GPIO hardware does not support double-edge triggering,
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or if this feature is diabled in the
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.Ar flag
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locator, then only ASSERT will be signaled on the specified edge.
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.Pp
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If two pins are specified, the first pin is used to trigger the
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ASSERT signal and the second pin is used to trigger the CLEAR
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signal.
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The ASSERT pin's trigger edge is specified by by the
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.Ar flag
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locator, and the CLEAR pin triggers on the opposite edge.
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This allows ASSERT and CLEAR signals to be triggered even if the underlying
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GPIO hardware does not support double-edge triggering.
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In this scenario, both GPIO pins would be connected in parallel to the
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device sending the 1PPS signals.
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.Pp
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The
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.Ar offset ,
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.Ar mask ,
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and
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.Ar flag
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locators can also be specified when
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.Nm
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is attached at runtime using the
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.Dv GPIOATTACH
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.Xr ioctl 2
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on the
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.Xr gpio 4
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device.
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.Sh SEE ALSO
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.Xr gpio 4 ,
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.Xr drvctl 8 ,
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.Xr gpioctl 8
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.Sh HISTORY
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The
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.Nm
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driver first appeared in
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.Nx 9.0 .
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.Sh AUTHORS
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.An -nosplit
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The
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.Nm
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driver was written by
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.An Brad Spencer Aq Mt brad@anduin.eldar.org .
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