102 lines
4.7 KiB
C
102 lines
4.7 KiB
C
/* $NetBSD: ncareg.h,v 1.1 1998/10/25 18:41:56 christos Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by John M. Ruschmeyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Definitions for 53C400 SCSI-controller chip.
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*
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* Derived from Linux NCR-5380 generic driver sources (by Drew Eckhardt).
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*
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* Copyright (C) 1994 Serge Vakulenko (vak@cronyx.ru)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE DEVELOPERS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE DEVELOPERS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* NCR5380 registers
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*/
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#define C80_CSDR 0 /* ro - Current SCSI Data Reg. */
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#define C80_ODR 0 /* wo - Output Data Reg. */
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#define C80_ICR 1 /* rw - Initiator Command Reg. */
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#define C80_MR 2 /* rw - Mode Reg. */
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#define C80_TCR 3 /* rw - Target Command Reg. */
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#define C80_CSBR 4 /* ro - Current SCSI Bus Status Reg. */
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#define C80_SER 4 /* wo - Select Enable Reg. */
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#define C80_BSR 5 /* ro - Bus and Status Reg. */
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#define C80_SDSR 5 /* wo - Start DMA Send Reg. */
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#define C80_IDR 6 /* ro - Input Data Reg. */
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#define C80_SDTR 6 /* wo - Start DMA Target Receive Reg. */
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#define C80_RPIR 7 /* ro - Reset Parity/Interrupt Reg. */
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#define C80_SDIR 7 /* wo - Start DMA Initiator Receive Reg. */
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#define C400_CSR 0 /* rw - Control and Status Reg. */
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# define C400_CSR_5380_ENABLE 0x80
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# define C400_CSR_TRANSFER_DIRECTION 0x40
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# define C400_CSR_TRANSFER_READY_INTR 0x20
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# define C400_CSR_5380_INTR 0x10
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# define C400_CSR_SHARED_INTR 0x08
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# define C400_CSR_HOST_BUF_NOT_READY 0x04 /* read only */
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# define C400_CSR_SCSI_BUF_READY 0x02 /* read only */
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# define C400_CSR_5380_GATED_IRQ 0x01 /* read only */
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# define C400_CSR_BITS "\20\1irq\2sbrdy\3hbrdy\4shintr\5intr\6tintr\7tdir\10enable"
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#define C400_CCR 1 /* rw - Clock Counter Reg. */
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#define C400_HBR 4 /* rw - Host Buffer Reg. */
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#define C400_5380_REG_OFFSET 8 /* Offset of 5380 registers. */
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