99 lines
4.4 KiB
C
99 lines
4.4 KiB
C
/* $NetBSD: nextdmareg.h,v 1.3 1998/12/27 09:03:15 dbj Exp $ */
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/*
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* Copyright (c) 1998 Darrin B. Jewell
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Darrin B. Jewell
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* I think the chip can handle 64k per chain, but I don't
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* know how much per segment for sure. We might try
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* experimenting with this value. Can we cross page boundaries?
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*/
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#define MAX_DMASIZE 8192
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/* from nextdev/dma.h */
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#define DMA_BEGINALIGNMENT 4 /* initial buffer must be on long */
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#define DMA_ENDALIGNMENT 16 /* DMA must end on quad longword */
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#define DMA_ALIGN(type, addr) \
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((type)(((unsigned)(addr)+DMA_BEGINALIGNMENT-1) \
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&~(DMA_BEGINALIGNMENT-1)))
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#define DMA_ENDALIGN(type, addr) \
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((type)(((unsigned)(addr)+DMA_ENDALIGNMENT-1) \
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&~(DMA_ENDALIGNMENT-1)))
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#define DMA_BEGINALIGNED(addr) (((unsigned)(addr)&(DMA_BEGINALIGNMENT-1))==0)
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#define DMA_ENDALIGNED(addr) (((unsigned)(addr)&(DMA_ENDALIGNMENT-1))==0)
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struct dma_dev { /* format of dma device registers */
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int dd_csr; /* control & status register */
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char dd_pad[0x3fec]; /* csr not contiguous with next */
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char *dd_saved_next; /* saved pointers for HW restart */
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char *dd_saved_limit;
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char *dd_saved_start;
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char *dd_saved_stop;
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char *dd_next; /* next word to dma */
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char *dd_limit; /* dma complete when next == limit */
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char *dd_start; /* start of 2nd buf to dma */
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char *dd_stop; /* end of 2nd buf to dma */
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char dd_pad2[0x1f0];
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char *dd_next_initbuf; /* next register that inits dma buffering */
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};
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#define DD_CSR 0
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#define DD_SAVED_NEXT (DD_CSR +sizeof(int) + 0x3fec)
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#define DD_SAVED_LIMIT (DD_SAVED_NEXT +sizeof(char *))
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#define DD_SAVED_START (DD_SAVED_LIMIT +sizeof(char *))
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#define DD_SAVED_STOP (DD_SAVED_START +sizeof(char *))
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#define DD_NEXT (DD_SAVED_STOP +sizeof(char *))
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#define DD_LIMIT (DD_NEXT +sizeof(char *))
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#define DD_START (DD_LIMIT +sizeof(char *))
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#define DD_STOP (DD_START +sizeof(char *))
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#define DD_NEXT_INITBUF (DD_STOP +sizeof(char *) + 0x1f0)
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/*
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* bits in dd_csr
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*/
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/* read bits */
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#define DMACSR_ENABLE 0x01000000 /* enable dma transfer */
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#define DMACSR_SUPDATE 0x02000000 /* single update */
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#define DMACSR_COMPLETE 0x08000000 /* current dma has completed */
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#define DMACSR_BUSEXC 0x10000000 /* bus exception occurred */
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/* write bits */
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#define DMACSR_SETENABLE 0x00010000 /* set enable */
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#define DMACSR_SETSUPDATE 0x00020000 /* set single update */
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#define DMACSR_READ 0x00040000 /* dma from dev to mem */
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#define DMACSR_WRITE 0x00000000 /* dma from mem to dev */
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#define DMACSR_CLRCOMPLETE 0x00080000 /* clear complete conditional */
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#define DMACSR_RESET 0x00100000 /* clr cmplt, sup, enable */
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#define DMACSR_INITBUF 0x00200000 /* initialize DMA buffers */
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#define DMACSR_BITS \
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"\20\35BUSEXC\34COMPLETE\32SUPDATE\31ENABLE\26INITBUF\25RESET\24CLRCOMPLETE\23READ\22SETSUPDATE\21SETENABLE"
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