423 lines
12 KiB
C
423 lines
12 KiB
C
/* $NetBSD: spdmem.c,v 1.6 2007/12/14 13:18:43 njoly Exp $ */
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/*
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* Copyright (c) 2007 Nicolas Joly
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* Copyright (c) 2007 Paul Goyette
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* Copyright (c) 2007 Tobias Nygren
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Serial Presence Detect (SPD) memory identification
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.6 2007/12/14 13:18:43 njoly Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/sysctl.h>
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#include <machine/bswap.h>
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#include <dev/i2c/i2cvar.h>
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#include <dev/i2c/spdmemreg.h>
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#include <dev/i2c/spdmemvar.h>
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static int spdmem_match(struct device *, struct cfdata *, void *);
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static void spdmem_attach(struct device *, struct device *, void *);
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SYSCTL_SETUP_PROTO(sysctl_spdmem_setup);
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static uint8_t spdmem_read(struct spdmem_softc *, uint8_t);
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CFATTACH_DECL(spdmem, sizeof(struct spdmem_softc),
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spdmem_match, spdmem_attach, NULL, NULL);
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#define IS_RAMBUS_TYPE (s->sm_len < 4)
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static const char* spdmem_basic_types[] = {
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"unknown",
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"FPM",
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"EDO",
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"Pipelined Nibble",
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"SDRAM",
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"ROM",
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"DDR SGRAM",
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"DDR SDRAM",
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"DDR2 SDRAM",
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"DDR2 SDRAM FB",
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"DDR2 SDRAM FB Probe"
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};
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static const char* spdmem_superset_types[] = {
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"unknown",
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"ESDRAM",
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"DDR ESDRAM",
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"PEM EDO",
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"PEM SDRAM"
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};
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static const char* spdmem_voltage_types[] = {
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"TTL (5V tolerant)",
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"LvTTL (not 5V tolerant)",
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"HSTL 1.5V",
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"SSTL 3.3V",
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"SSTL 2.5V",
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"SSTL 1.8V"
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};
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static const char* spdmem_refresh_types[] = {
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"15.625us",
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"3.9us",
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"7.8us",
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"31.3us",
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"62.5us",
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"125us"
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};
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static const char* spdmem_parity_types[] = {
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"no parity or ECC",
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"data parity",
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"data ECC",
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"data parity and ECC",
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"cmd/addr parity",
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"cmd/addr/data parity",
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"cmd/addr parity, data ECC",
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"cmd/addr/data parity, data ECC"
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};
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/* Cycle time fractional values for DDR2 SDRAM */
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static const uint8_t spdmem_cycle_frac[] = {
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0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 25, 33, 67, 75, 99, 99
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};
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/* sysctl stuff */
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static int hw_node = CTL_EOL;
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static int
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spdmem_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct i2c_attach_args *ia = aux;
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struct spdmem_softc sc;
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int cksum = 0;
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uint8_t i, val;
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if (ia->ia_addr < 0x50 || ia->ia_addr > 0x57)
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return 0;
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sc.sc_tag = ia->ia_tag;
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sc.sc_addr = ia->ia_addr;
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for (i = 0; i < 63; i++)
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cksum += spdmem_read(&sc, i);
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val = spdmem_read(&sc, 63);
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if (cksum == 0 || (cksum & 0xff) != val)
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return 0;
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return 1;
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}
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static void
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spdmem_attach(struct device *parent, struct device *self, void *aux)
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{
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struct spdmem_softc *sc = device_private(self);
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struct i2c_attach_args *ia = aux;
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struct spdmem *s = &(sc->sc_spd_data);
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const char *type;
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const char *voltage;
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const char *refresh;
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const char *ddr_type_string = NULL;
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int num_banks = 0;
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int per_chip = 0;
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int dimm_size, cycle_time, d_clk, p_clk, bits;
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int i;
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const struct sysctlnode *node = NULL;
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sc->sc_tag = ia->ia_tag;
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sc->sc_addr = ia->ia_addr;
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/* All SPD have at least 64 bytes of data including checksum */
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for (i = 0; i < 64; i++) {
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((uint8_t *)s)[i] = spdmem_read(sc, i);
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}
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#ifdef DEBUG
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for (i = 0; i < 64; i += 16) {
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int j;
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aprint_debug("\n%s: 0x%02x:", self->dv_xname, i);
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for(j = 0; j < 16; j++)
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aprint_debug(" %02x", ((uint8_t *)s)[i + j]);
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}
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aprint_debug("\n%s", self->dv_xname);
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#endif
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/*
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* Setup our sysctl subtree, hw.spdmemN
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*/
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if (hw_node != CTL_EOL)
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sysctl_createv(NULL, 0, NULL, &node,
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0, CTLTYPE_NODE,
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self->dv_xname, NULL, NULL, 0, NULL, 0,
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CTL_HW, CTL_CREATE, CTL_EOL);
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if (node != NULL)
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sysctl_createv(NULL, 0, NULL, NULL,
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0,
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CTLTYPE_STRUCT, "spd_data",
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SYSCTL_DESCR("raw spd data (first 64 bytes)"), NULL,
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0, s, sizeof(*s),
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CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL);
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/*
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* Decode and print SPD contents
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*/
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if (IS_RAMBUS_TYPE)
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type = "Rambus";
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else {
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if (s->sm_type <= 10)
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type = spdmem_basic_types[s->sm_type];
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else
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type = "unknown memory type";
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if (s->sm_type == SPDMEM_MEMTYPE_EDO &&
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s->sm_fpm.fpm_superset == SPDMEM_SUPERSET_EDO_PEM)
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type = spdmem_superset_types[SPDMEM_SUPERSET_EDO_PEM];
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if (s->sm_type == SPDMEM_MEMTYPE_SDRAM &&
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s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_SDRAM_PEM)
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type = spdmem_superset_types[SPDMEM_SUPERSET_SDRAM_PEM];
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if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM &&
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s->sm_ddr.ddr_superset == SPDMEM_SUPERSET_DDR_ESDRAM)
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type =
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spdmem_superset_types[SPDMEM_SUPERSET_DDR_ESDRAM];
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if (s->sm_type == SPDMEM_MEMTYPE_SDRAM &&
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s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_ESDRAM) {
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type = spdmem_superset_types[SPDMEM_SUPERSET_ESDRAM];
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}
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}
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aprint_normal("\n%s: %s memory", self->dv_xname, type);
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strlcpy(sc->sc_type, type, SPDMEM_TYPE_MAXLEN);
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if (node != NULL)
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sysctl_createv(NULL, 0, NULL, NULL,
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0,
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CTLTYPE_STRING, "mem_type",
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SYSCTL_DESCR("memory module type"), NULL,
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0, sc->sc_type, 0,
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CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL);
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if ((s->sm_type == SPDMEM_MEMTYPE_SDRAM ||
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s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM ||
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s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM ) &&
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s->sm_config < 8)
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aprint_normal(", %s", spdmem_parity_types[s->sm_config]);
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dimm_size = 0;
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if (IS_RAMBUS_TYPE) {
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aprint_normal(", %dMB",
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1 << (s->sm_rdr.rdr_rows + s->sm_rdr.rdr_cols - 13));
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} else if (s->sm_type == SPDMEM_MEMTYPE_SDRAM) {
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dimm_size = s->sm_sdr.sdr_rows + s->sm_sdr.sdr_cols - 17;
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num_banks = s->sm_sdr.sdr_banks;
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per_chip = s->sm_sdr.sdr_banks_per_chip;
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} else if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM) {
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dimm_size = s->sm_ddr.ddr_rows + s->sm_ddr.ddr_cols - 17;
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num_banks = s->sm_ddr.ddr_ranks;
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per_chip = s->sm_ddr.ddr_banks_per_chip;
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} else if (s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM) {
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dimm_size = s->sm_ddr2.ddr2_rows + s->sm_ddr2.ddr2_cols - 17;
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num_banks = s->sm_ddr2.ddr2_ranks + 1;
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per_chip = s->sm_ddr2.ddr2_banks_per_chip;
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}
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if (!(IS_RAMBUS_TYPE) && num_banks <= 8 && per_chip <= 8 &&
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dimm_size > 0 && dimm_size <= 12) {
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dimm_size = (1 << dimm_size) * num_banks * per_chip;
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aprint_normal(", %dMB", dimm_size);
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if (node != NULL)
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sysctl_createv(NULL, 0, NULL, NULL,
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CTLFLAG_IMMEDIATE,
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CTLTYPE_INT, "size",
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SYSCTL_DESCR("module size in MB"), NULL,
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dimm_size, NULL, 0,
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CTL_HW, node->sysctl_num, CTL_CREATE,
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CTL_EOL);
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}
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/* cycle_time is expressed in units of 0.01 ns */
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cycle_time = 0;
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if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM ||
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s->sm_type == SPDMEM_MEMTYPE_SDRAM)
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cycle_time = s->sm_ddr.ddr_cycle_whole * 100 +
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s->sm_ddr.ddr_cycle_tenths * 10;
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else if (s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM) {
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cycle_time = s->sm_ddr2.ddr2_cycle_whole * 100 +
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spdmem_cycle_frac[s->sm_ddr2.ddr2_cycle_frac];
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}
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if (cycle_time != 0) {
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/*
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* cycle time is scaled by a factor of 100 to avoid using
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* floating point. Calculate memory speed as the number
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* of cycles per microsecond.
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*/
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d_clk = 100 * 1000;
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if (s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM) {
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/* DDR2 uses quad-pumped clock */
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d_clk *= 4;
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bits = s->sm_ddr2.ddr2_datawidth;
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if ((s->sm_config & 0x03) != 0)
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bits -= 8;
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ddr_type_string = "PC2";
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} else if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM) {
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/* DDR uses dual-pumped clock */
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d_clk *= 2;
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#if BYTE_ORDER == BIG_ENDIAN
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bits = bswap16(s->sm_ddr.ddr_datawidth);
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#else
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bits = s->sm_ddr.ddr_datawidth;
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#endif
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if (s->sm_config == 1 || s->sm_config == 2)
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bits -= 8;
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ddr_type_string = "PC";
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} else { /* SPDMEM_MEMTYPE_SDRAM */
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#if BYTE_ORDER == BIG_ENDIAN
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bits = bswap16(s->sm_ddr.ddr_datawidth);
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#else
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bits = s->sm_ddr.ddr_datawidth;
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#endif
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if (s->sm_config == 1 || s->sm_config == 2)
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bits -= 8;
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ddr_type_string = "PC";
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}
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d_clk /= cycle_time;
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if (s->sm_type == SPDMEM_MEMTYPE_DDR2SDRAM)
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d_clk = (d_clk + 1) / 2;
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p_clk = d_clk * bits / 8;
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if ((p_clk % 100) >= 50)
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p_clk += 50;
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p_clk -= p_clk % 100;
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aprint_normal(", %dMHz, %s-%d", d_clk, ddr_type_string, p_clk);
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if (node != NULL)
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sysctl_createv(NULL, 0, NULL, NULL,
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CTLFLAG_IMMEDIATE,
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CTLTYPE_INT, "speed",
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SYSCTL_DESCR("memory speed in MHz"), NULL,
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d_clk, NULL, 0,
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CTL_HW, node->sysctl_num, CTL_CREATE,
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CTL_EOL);
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}
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aprint_normal("\n");
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aprint_verbose("%s: ", self->dv_xname);
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switch (s->sm_type) {
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case SPDMEM_MEMTYPE_EDO:
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case SPDMEM_MEMTYPE_FPM:
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aprint_verbose(
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"%d rows, %d cols, %d banks, %dns tRAC, %dns tCAC\n",
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s->sm_fpm.fpm_rows, s->sm_fpm.fpm_cols,
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s->sm_fpm.fpm_banks, s->sm_fpm.fpm_tRAC,
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s->sm_fpm.fpm_tCAC);
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break;
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case SPDMEM_MEMTYPE_ROM:
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aprint_verbose("%d rows, %d cols, %d banks\n",
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s->sm_rom.rom_rows, s->sm_rom.rom_cols,
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s->sm_rom.rom_banks);
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break;
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case SPDMEM_MEMTYPE_SDRAM:
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aprint_verbose(
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"%d rows, %d cols, %d banks, %d banks/chip, "
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"%d.%dns cycle time\n",
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s->sm_sdr.sdr_rows, s->sm_sdr.sdr_cols, s->sm_sdr.sdr_banks,
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s->sm_sdr.sdr_banks_per_chip, s->sm_sdr.sdr_cycle_whole,
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s->sm_sdr.sdr_cycle_tenths);
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break;
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case SPDMEM_MEMTYPE_DDRSDRAM:
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aprint_verbose(
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"%d rows, %d cols, %d ranks, %d banks/chip, "
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"%d.%dns cycle time\n",
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s->sm_ddr.ddr_rows, s->sm_ddr.ddr_cols, s->sm_ddr.ddr_ranks,
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s->sm_ddr.ddr_banks_per_chip, s->sm_ddr.ddr_cycle_whole,
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s->sm_ddr.ddr_cycle_tenths);
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break;
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case SPDMEM_MEMTYPE_DDR2SDRAM:
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aprint_verbose(
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"%d rows, %d cols, %d ranks, %d banks/chip, "
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"%d.%02dns cycle time\n",
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s->sm_ddr2.ddr2_rows, s->sm_ddr2.ddr2_cols,
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s->sm_ddr2.ddr2_ranks + 1, s->sm_ddr2.ddr2_banks_per_chip,
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s->sm_ddr2.ddr2_cycle_whole,
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spdmem_cycle_frac[s->sm_ddr2.ddr2_cycle_frac]);
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break;
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default:
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break;
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}
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if (s->sm_voltage <= 0x5)
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voltage = spdmem_voltage_types[s->sm_voltage];
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else
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voltage = "unknown";
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if (s->sm_refresh <= 0x05)
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refresh = spdmem_refresh_types[s->sm_refresh];
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else
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refresh = "unknown";
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aprint_verbose("%s: voltage %s, refresh time %s", self->dv_xname,
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voltage, refresh);
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if (s->sm_selfrefresh)
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aprint_verbose(" (self-refreshing)");
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aprint_verbose("\n");
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if (!pmf_device_register(self, NULL, NULL))
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aprint_error_dev(self, "couldn't establish power handler\n");
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}
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static uint8_t
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spdmem_read(struct spdmem_softc *sc, uint8_t reg)
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{
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uint8_t val;
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iic_acquire_bus(sc->sc_tag,0);
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iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, ®, 1,
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&val, 1, 0);
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iic_release_bus(sc->sc_tag, 0);
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return val;
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}
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SYSCTL_SETUP(sysctl_spdmem_setup, "sysctl hw.spdmem subtree setup")
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{
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const struct sysctlnode *node;
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if (sysctl_createv(clog, 0, NULL, &node,
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CTLFLAG_PERMANENT,
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CTLTYPE_NODE, "hw", NULL,
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NULL, 0, NULL, 0,
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CTL_HW, CTL_EOL) != 0)
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return;
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hw_node = node->sysctl_num;
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}
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