876 lines
23 KiB
C
876 lines
23 KiB
C
/* $NetBSD: edc_mca.c,v 1.9 2001/05/04 12:58:34 jdolecek Exp $ */
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/*
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jaromir Dolecek.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for MCA ESDI controllers and disks conforming to IBM DASD
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* spec.
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*
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* The driver was written with DASD Storage Interface Specification
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* for MCA rev. 2.2 in hands, thanks to Scott Telford <st@epcc.ed.ac.uk>.
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*
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* TODO:
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* - move the MCA DMA controller (edc_setup_dma()) goo to device driver
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* independant location
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* - improve error recovery
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* add any soft resets when anything gets stuck?
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* - test with > 1 disk (this is supported by some controllers), eliminate
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* any remaining devno=0 assumptions if there are any still
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* - test with > 1 ESDI controller in machine; shared interrupts
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* necessary for this to work should be supported - edc_intr() specifically
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* checks if the interrupt is for this controller
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*/
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#include "rnd.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/endian.h>
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#include <sys/disklabel.h>
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#include <sys/disk.h>
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#include <sys/syslog.h>
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#include <sys/proc.h>
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#include <sys/vnode.h>
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#include <sys/kernel.h>
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#if NRND > 0
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#include <sys/rnd.h>
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#endif
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/mca/mcareg.h>
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#include <dev/mca/mcavar.h>
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#include <dev/mca/mcadevs.h>
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#include <dev/mca/edcreg.h>
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#include <dev/mca/edvar.h>
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#include <dev/mca/edcvar.h>
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#define EDC_ATTN_MAXTRIES 10000 /* How many times check for unbusy */
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struct edc_mca_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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bus_dma_tag_t sc_dmat; /* DMA tag as passed by parent */
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bus_space_handle_t sc_dmaextcmdh;
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bus_space_handle_t sc_dmaexech;
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void *sc_ih; /* interrupt handle */
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int sc_drq; /* DRQ number */
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int sc_cmd_async; /* asynchronous cmd pending */
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int sc_flags;
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#define DASD_QUIET 0x01 /* don't dump cmd error info */
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#define DASD_MAXDEVS 8
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struct ed_softc *sc_ed[DASD_MAXDEVS];
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struct ed_softc sc_controller;
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};
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int edc_mca_probe __P((struct device *, struct cfdata *, void *));
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void edc_mca_attach __P((struct device *, struct device *, void *));
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struct cfattach edc_mca_ca = {
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sizeof(struct edc_mca_softc), edc_mca_probe, edc_mca_attach
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};
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#define DMA_EXTCMD 0x18
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#define DMA_EXEC 0x1A
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static int edc_intr __P((void *));
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static void edc_dump_status_block __P((struct edc_mca_softc *, int, int));
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static int edc_setup_dma __P((struct edc_mca_softc *, int,
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bus_addr_t, bus_size_t));
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static int edc_do_attn __P((struct edc_mca_softc *, int, int, int));
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static int edc_cmd_wait __P((struct edc_mca_softc *, int, int, int));
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int
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edc_mca_probe(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct mca_attach_args *ma = aux;
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switch (ma->ma_id) {
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case MCA_PRODUCT_IBM_ESDIC:
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case MCA_PRODUCT_IBM_ESDIC_IG:
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return (1);
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default:
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return (0);
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}
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}
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void
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edc_mca_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct edc_mca_softc *sc = (void *) self;
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struct mca_attach_args *ma = aux;
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int pos2, pos3, pos4;
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int irq, drq, iobase;
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const char *typestr;
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struct ed_softc *ed;
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struct ed_attach_args eda;
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int devno, maxdevs;
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pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2);
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pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3);
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pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4);
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/*
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* POS register 2: (adf pos0)
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*
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* 7 6 5 4 3 2 1 0
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* \ \____/ \ \__ enable: 0=adapter disabled, 1=adapter enabled
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* \ \ \___ Primary/Alternate Port Adresses:
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* \ \ 0=0x3510-3517 1=0x3518-0x351f
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* \ \_____ DMA Arbitration Level: 0101=5 0110=6 0111=7
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* \ 0000=0 0001=1 0011=3 0100=4
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* \_________ Fairness On/Off: 1=On 0=Off
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*
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* POS register 3: (adf pos1)
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*
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* 7 6 5 4 3 2 1 0
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* 0 0 \_/
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* \__________ DMA Burst Pacing Interval: 10=24ms 11=31ms
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* 01=16ms 00=Burst Disabled
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*
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* POS register 4: (adf pos2)
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*
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* 7 6 5 4 3 2 1 0
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* \_/ \__ DMA Pacing Control: 1=Disabled 0=Enabled
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* \____ Time to Release: 1X=6ms 01=3ms 00=Immediate
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*
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* IRQ is fixed to 14 (0x0e).
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*/
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switch (ma->ma_id) {
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case MCA_PRODUCT_IBM_ESDIC:
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typestr = "IBM ESDI Fixed Disk Controller";
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break;
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case MCA_PRODUCT_IBM_ESDIC_IG:
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typestr = "IBM Integ. ESDI Fixed Disk & Controller";
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break;
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default:
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/* never reached */
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}
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irq = ESDIC_IRQ;
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iobase = (pos2 & IO_IS_ALT) ? ESDIC_IOALT : ESDIC_IOPRM;
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drq = (pos2 & DRQ_MASK) >> 2;
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printf(" slot %d irq %d drq %d: %s\n", ma->ma_slot+1,
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irq, drq, typestr);
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#ifdef DIAGNOSTIC
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/*
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* It's not strictly necessary to check this, machine configuration
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* utility uses only valid adresses.
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*/
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if (drq == 2 || drq >= 8) {
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printf("%s: invalid DMA Arbitration Level %d\n",
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sc->sc_dev.dv_xname, drq);
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return;
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}
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#endif
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printf("%s: Fairness %s, Release %s, ",
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sc->sc_dev.dv_xname,
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(pos2 & FAIRNESS_ENABLE) ? "On" : "Off",
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(pos4 & RELEASE_1) ? "6ms"
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: ((pos4 & RELEASE_2) ? "3ms" : "Immediate")
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);
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if ((pos4 & PACING_CTRL_DISABLE) == 0) {
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static const char * const pacint[] =
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{ "disabled", "16ms", "24ms", "31ms"};
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printf("DMA burst pacing interval %s\n",
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pacint[(pos3 & PACING_INT_MASK) >> 4]);
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} else
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printf("DMA pacing control disabled\n");
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sc->sc_iot = ma->ma_iot;
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sc->sc_drq = drq;
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if (bus_space_map(sc->sc_iot, iobase,
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ESDIC_REG_NPORTS, 0, &sc->sc_ioh)) {
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printf("%s: couldn't map registers\n",
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sc->sc_dev.dv_xname);
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return;
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}
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if (bus_space_map(sc->sc_iot, DMA_EXTCMD, 1, 0, &sc->sc_dmaextcmdh)) {
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printf("%s: couldn't map registers\n",
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sc->sc_dev.dv_xname);
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return;
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}
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if (bus_space_map(sc->sc_iot, DMA_EXEC, 1, 0, &sc->sc_dmaexech)) {
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printf("%s: couldn't map registers\n",
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sc->sc_dev.dv_xname);
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return;
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}
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sc->sc_dmat = ma->ma_dmat;
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sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, edc_intr, sc);
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if (sc->sc_ih == NULL) {
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printf("%s: couldn't establish interrupt handler\n",
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sc->sc_dev.dv_xname);
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return;
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}
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/*
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* Integrated ESDI controller supports only one disk, other
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* controllers support two disks.
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*/
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if (ma->ma_id == MCA_PRODUCT_IBM_ESDIC_IG)
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maxdevs = 1;
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else
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maxdevs = 2;
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/*
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* Initialize the controller ed softc. We could do without this,
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* but absence of checks for controller devno simplifies code logic
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* somewhat.
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*/
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sc->sc_ed[DASD_DEVNO_CONTROLLER] = &sc->sc_controller;
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strcpy(sc->sc_controller.sc_dev.dv_xname, sc->sc_dev.dv_xname);/*safe*/
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/*
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* Reset controller and attach individual disks. ed attach routine
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* uses polling so that this works with interrupts disabled.
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*/
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/* Do a reset to ensure sane state after warm boot. */
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if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) {
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/* hard reset */
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printf("%s: controller busy, performing hardware reset ...\n",
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sc->sc_dev.dv_xname);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR,
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BCR_INT_ENABLE|BCR_RESET);
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} else {
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/* "SOFT" reset */
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edc_do_attn(sc, ATN_RESET_ATTACHMENT, DASD_DEVNO_CONTROLLER,0);
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}
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/*
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* Since interrupts are disabled ATM, it's necessary
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* to detect the interrupt request and call edc_intr()
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* explicitly. See also edc_run_cmd().
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*/
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while(bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_BUSY) {
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if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR)
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edc_intr(sc);
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delay(100);
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}
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/*
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* Get dummy ed_softc to be used during probe. Once a disk is
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* found, ed_mca_attach() calls edc_add_disk() to insert the
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* right pointer into sc->sc_ed[] array.
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*/
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MALLOC(ed, struct ed_softc *, sizeof(struct ed_softc),
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M_TEMP, M_WAITOK);
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/* be quiet duting probes */
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sc->sc_flags |= DASD_QUIET;
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/* check for attached disks */
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for(devno=0; devno < maxdevs; devno++) {
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eda.sc_devno = devno;
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eda.sc_dmat = sc->sc_dmat;
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sc->sc_ed[devno] = ed;
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(void *) config_found_sm(self, &eda, NULL, NULL);
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}
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/* enable full error dumps again */
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sc->sc_flags &= ~DASD_QUIET;
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/* cleanup */
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FREE(ed, M_TEMP);
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/*
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* Check if there are any disks attached. If not, disestablish
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* the interrupt.
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*/
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for(devno=0; devno < maxdevs; devno++) {
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if (sc->sc_ed[devno] && (sc->sc_ed[devno]->sc_flags & EDF_INIT))
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break;
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}
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if (devno == maxdevs) {
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printf("%s: disabling controller (no drives attached)\n",
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sc->sc_dev.dv_xname);
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mca_intr_disestablish(ma->ma_mc, sc->sc_ih);
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}
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}
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void
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edc_add_disk(sc, ed, devno)
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struct edc_mca_softc *sc;
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struct ed_softc *ed;
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int devno;
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{
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sc->sc_ed[devno] = ed;
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}
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static int
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edc_intr(arg)
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void *arg;
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{
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struct edc_mca_softc *sc = arg;
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u_int8_t isr, intr_id;
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u_int16_t sifr;
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int cmd=-1, devno, bioerror=0;
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struct ed_softc *ed=NULL;
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/*
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* Check if the interrupt was for us.
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*/
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if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_INTR) == 0)
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return (0);
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/*
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* Read ISR to find out interrupt type. This also clears the interrupt
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* condition and BSR_INTR flag. Accordings to docs interrupt ID of 0, 2
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* and 4 are reserved and not used.
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*/
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isr = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ISR);
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intr_id = isr & ISR_INTR_ID_MASK;
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#ifdef DEBUG
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if (intr_id == 0 || intr_id == 2 || intr_id == 4) {
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printf("%s: bogus interrupt id %d\n", sc->sc_dev.dv_xname,
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(int) intr_id);
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return (0);
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}
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#endif
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/* Get number of device whose intr this was */
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devno = (isr & 0xe0) >> 5;
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/*
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* Get Status block. Higher byte always says how long the status
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* block is, rest is device number and command code.
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* Check the status block length against our supported maximum length
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* and fetch the data.
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*/
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if (bus_space_read_1(sc->sc_iot, sc->sc_ioh,BSR) & BSR_SIFR_FULL) {
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size_t len;
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int i;
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sifr = le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR));
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len = (sifr & 0xff00) >> 8;
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#ifdef DEBUG
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if (len > DASD_MAX_CMD_RES_LEN)
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panic("%s: maximum Status Length exceeded: %d > %d",
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sc->sc_dev.dv_xname,
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len, DASD_MAX_CMD_RES_LEN);
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#endif
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/* Get command code */
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cmd = sifr & SIFR_CMD_MASK;
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/* Read whole status block */
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ed = sc->sc_ed[devno];
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ed->sc_status_block[0] = sifr;
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for(i=1; i < len; i++) {
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while((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)
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& BSR_SIFR_FULL) == 0)
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delay(1);
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ed->sc_status_block[i] = le16toh(
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bus_space_read_2(sc->sc_iot, sc->sc_ioh, SIFR));
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}
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}
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switch (intr_id) {
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case ISR_DATA_TRANSFER_RDY:
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/*
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* Ready to do DMA, setup DMA controller and kick DASD
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* controller to do the transfer.
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*/
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ed = sc->sc_ed[devno];
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if (!edc_setup_dma(sc, ed->sc_read,
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ed->dmamap_xfer->dm_segs[0].ds_addr,
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ed->dmamap_xfer->dm_segs[0].ds_len)) {
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/* XXX bail out? */
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printf("%s: edc_setup_dma() failed\n",
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ed->sc_dev.dv_xname);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR,
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BCR_INT_ENABLE);
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} else {
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/* OK, proceed with DMA */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR,
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BCR_INT_ENABLE|BCR_DMA_ENABLE);
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}
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break;
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case ISR_COMPLETED:
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case ISR_COMPLETED_WITH_ECC:
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case ISR_COMPLETED_RETRIES:
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case ISR_COMPLETED_WARNING:
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bioerror = 0;
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break;
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case ISR_RESET_COMPLETED:
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case ISR_ABORT_COMPLETED:
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/* nothing to do */
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break;
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default:
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if ((sc->sc_flags & DASD_QUIET) == 0)
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edc_dump_status_block(sc, devno, intr_id);
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bioerror = EIO;
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break;
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}
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/*
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* Unless the interrupt is for Data Transfer Ready or
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* Attention Error, finish by assertion EOI. This makes
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* attachment aware the interrupt is processed and system
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* is ready to accept another one.
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*/
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if (intr_id != ISR_DATA_TRANSFER_RDY && intr_id != ISR_ATTN_ERROR)
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edc_do_attn(sc, ATN_END_INT, devno, intr_id);
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/* If Read or Write Data, wakeup worker thread to finish it */
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if (intr_id != ISR_DATA_TRANSFER_RDY
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&& (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA)) {
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sc->sc_ed[devno]->sc_error = bioerror;
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wakeup_one(&sc->sc_ed[devno]->edc_softc);
|
|
}
|
|
|
|
return (1);
|
|
}
|
|
|
|
/*
|
|
* This follows the exact order for Attention Request as
|
|
* written in DASD Storage Interface Specification MC (Rev 2.2).
|
|
*/
|
|
static int
|
|
edc_do_attn(sc, attn_type, devno, intr_id)
|
|
struct edc_mca_softc *sc;
|
|
int attn_type, devno, intr_id;
|
|
{
|
|
int tries;
|
|
|
|
/* 1. Disable interrupts in BCR. */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, 0);
|
|
|
|
/*
|
|
* 2. Assure NOT BUSY and NO INTERRUPT PENDING, unless acknowledging
|
|
* a RESET COMPLETED interrupt.
|
|
*/
|
|
if (intr_id != ISR_RESET_COMPLETED) {
|
|
for(tries=1; tries < EDC_ATTN_MAXTRIES; tries++) {
|
|
if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR)
|
|
& BSR_BUSY) == 0) {
|
|
#ifdef DEBUG
|
|
if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh,
|
|
BSR) & BSR_INT_PENDING) && intr_id)
|
|
panic("foobar");
|
|
#endif
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (tries == EDC_ATTN_MAXTRIES) {
|
|
printf("%s: edc_do_attn: timeout waiting for attachment to become available\n",
|
|
sc->sc_ed[devno]->sc_dev.dv_xname);
|
|
return (EAGAIN);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* 3. Write proper DEVICE NUMBER and Attention number to ATN.
|
|
*/
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, ATN,
|
|
attn_type | (devno << 5));
|
|
|
|
/*
|
|
* 4. Enable interrupts via BCR.
|
|
*/
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, BCR, BCR_INT_ENABLE);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Wait until command is processed, timeout after 'secs' seconds.
|
|
* We use mono_time, since we don't need actual RTC, just time
|
|
* interval.
|
|
*/
|
|
static int
|
|
edc_cmd_wait(sc, devno, secs, poll)
|
|
struct edc_mca_softc *sc;
|
|
int devno, secs, poll;
|
|
{
|
|
int val, delayed;
|
|
|
|
delayed = 0;
|
|
do {
|
|
val = bus_space_read_1(sc->sc_iot,sc->sc_ioh, BSR);
|
|
if ((val & BSR_CMD_INPROGRESS) == 0)
|
|
break;
|
|
|
|
if (poll && (val & BSR_INTR))
|
|
goto out;
|
|
|
|
if (secs == 0)
|
|
break;
|
|
|
|
delay(1);
|
|
|
|
/*
|
|
* This is not as accurate as checking mono_time, but
|
|
* it works with hardclock interrupts disabled too.
|
|
*/
|
|
delayed++;
|
|
if (delayed == 1000000) {
|
|
delayed = 0;
|
|
secs--;
|
|
}
|
|
#if 0
|
|
if (delayed % 1000)
|
|
printf("looping ...");
|
|
#endif
|
|
} while(1);
|
|
|
|
if (secs == 0 &&
|
|
bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_CMD_INPROGRESS){
|
|
printf("%s: timed out waiting for previous cmd to finish\n",
|
|
sc->sc_ed[devno]->sc_dev.dv_xname);
|
|
return (EAGAIN);
|
|
}
|
|
|
|
out:
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
edc_run_cmd(sc, cmd, devno, cmd_args, cmd_len, async, poll)
|
|
struct edc_mca_softc *sc;
|
|
int cmd;
|
|
int devno;
|
|
u_int16_t cmd_args[];
|
|
int cmd_len, async, poll;
|
|
{
|
|
int i, error, tries;
|
|
u_int16_t cmd0;
|
|
|
|
/*
|
|
* If there has been an asynchronous command executed, first wait for it
|
|
* to finish.
|
|
*/
|
|
if (sc->sc_cmd_async) {
|
|
/* Wait maximum 15s */
|
|
if (edc_cmd_wait(sc, devno, 15, 0))
|
|
return (EAGAIN); /* Busy */
|
|
|
|
sc->sc_cmd_async = 0;
|
|
}
|
|
|
|
/* Do Attention Request for Command Request. */
|
|
if ((error = edc_do_attn(sc, ATN_CMD_REQ, devno, 0)))
|
|
return (error);
|
|
|
|
/*
|
|
* Construct the command. The bits are like this:
|
|
*
|
|
* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
|
|
* \_/ 0 0 1 0 \__/ \_____/
|
|
* \ \__________/ \ \_ Command Code (see CMD_*)
|
|
* \ \ \__ Device: 0 common, 7 controller
|
|
* \ \__ Options: reserved, bit 10=cache bypass bit
|
|
* \_ Type: 00=2B, 01=4B, 10 and 11 reserved
|
|
*
|
|
* We always use device 0 or 1, so difference is made only by Command
|
|
* Code, Command Options and command length.
|
|
*/
|
|
cmd0 = ((cmd_len == 4) ? (CIFR_LONG_CMD) : 0)
|
|
| (devno << 5)
|
|
| (cmd_args[0] << 8) | cmd;
|
|
cmd_args[0] = cmd0;
|
|
|
|
/*
|
|
* Write word of CMD to the CIFR. This sets "Command
|
|
* Interface Register Full (CMD IN)" in BSR. Once the attachment
|
|
* detects it, it reads the word and clears CMD IN.
|
|
*/
|
|
for(i=0; i < cmd_len; i++) {
|
|
bus_space_write_2(sc->sc_iot, sc->sc_ioh, CIFR,
|
|
htole16(cmd_args[i]));
|
|
|
|
/*
|
|
* Wait until CMD IN is cleared. The 1ms delay for polling
|
|
* case is necessary, otherwise e.g. system dump gets stuck
|
|
* soon. Quirky hw ?
|
|
*/
|
|
tries = 0;
|
|
while(bus_space_read_1(sc->sc_iot, sc->sc_ioh, BSR) & BSR_CIFR_FULL)
|
|
delay(poll ? 1000 : 1);
|
|
}
|
|
|
|
/*
|
|
* Attachment is now executing the command. Unless we are executing
|
|
* command asynchronously, wait until it finishes.
|
|
*/
|
|
if (async) {
|
|
sc->sc_cmd_async = 1;
|
|
return (0);
|
|
}
|
|
|
|
/* Wait for command to complete, but maximum 15 seconds. */
|
|
if (edc_cmd_wait(sc, devno, 15, poll))
|
|
return (EAGAIN);
|
|
|
|
/* If polling, call edc_intr() explicitly */
|
|
if (poll) {
|
|
edc_intr(sc);
|
|
|
|
/*
|
|
* If got attention id DATA TRANSFER READY, wait for
|
|
* the transfer to finish.
|
|
*/
|
|
if (sc->sc_ed[devno]->sc_error == 0
|
|
&& (cmd == CMD_READ_DATA || cmd == CMD_WRITE_DATA)) {
|
|
if (edc_cmd_wait(sc, devno, 15, 1))
|
|
return (EAGAIN);
|
|
edc_intr(sc);
|
|
}
|
|
|
|
if (edc_cmd_wait(sc, devno, 15, 0))
|
|
return (EAGAIN);
|
|
}
|
|
|
|
/* Check if the command completed successfully; if not, return error */
|
|
switch(SB_GET_CMD_STATUS(sc->sc_ed[devno]->sc_status_block)) {
|
|
case ISR_COMPLETED:
|
|
case ISR_COMPLETED_WITH_ECC:
|
|
case ISR_COMPLETED_RETRIES:
|
|
case ISR_COMPLETED_WARNING:
|
|
return (0);
|
|
default:
|
|
return (EIO);
|
|
}
|
|
}
|
|
|
|
static int
|
|
edc_setup_dma(sc, isread, phys, cnt)
|
|
struct edc_mca_softc *sc;
|
|
int isread;
|
|
bus_addr_t phys;
|
|
bus_size_t cnt;
|
|
{
|
|
/* XXX magic constants, should be moved to device-independant location*/
|
|
/* The exact sequence to setup MCA DMA controller is taken from Minix */
|
|
|
|
bus_space_write_1(sc->sc_iot, sc->sc_dmaextcmdh, 0,
|
|
0x90 + sc->sc_drq);
|
|
/* Disable access to dma channel */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_dmaextcmdh, 0,
|
|
0x20 + sc->sc_drq);
|
|
/* Clear the address byte pointer */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_dmaexech, 0,
|
|
(phys >> 0) & 0xff); /* address bits 0..7 */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_dmaexech, 0,
|
|
(phys >> 8) & 0xff); /* address bits 8..15 */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_dmaexech, 0,
|
|
(phys >> 16) & 0xff); /* address bits 16..23 */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_dmaextcmdh, 0,
|
|
0x40 + sc->sc_drq);
|
|
/* Clear the count byte pointer */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_dmaexech, 0,
|
|
((cnt - 1) >> 0) & 0xff); /* count bits 0..7 */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_dmaexech, 0,
|
|
((cnt - 1) >> 8) & 0xff); /* count bits 8..15 */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_dmaextcmdh, 0,
|
|
0x70 + sc->sc_drq);
|
|
/* Set the transfer mode */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_dmaexech, 0,
|
|
(isread) ? 0x4C : 0x44);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_dmaextcmdh, 0,
|
|
0xA0 + sc->sc_drq);
|
|
/* Enable access to dma channel */
|
|
|
|
return (1);
|
|
}
|
|
|
|
static const char * const edc_commands[] = {
|
|
"Invalid Command",
|
|
"Read Data",
|
|
"Write Data",
|
|
"Read Verify",
|
|
"Write with Verify",
|
|
"Seek",
|
|
"Park Head",
|
|
"Get Command Complete Status",
|
|
"Get Device Status",
|
|
"Get Device Configuration",
|
|
"Get POS Information",
|
|
"Translate RBA",
|
|
"Write Attachment Buffer",
|
|
"Read Attachment Buffer",
|
|
"Run Diagnostic Test",
|
|
"Get Diagnostic Status Block",
|
|
"Get MFG Header",
|
|
"Format Unit",
|
|
"Format Prepare",
|
|
"Set MAX RBA",
|
|
"Set Power Saving Mode",
|
|
"Power Conservation Command",
|
|
};
|
|
|
|
static const char * const edc_cmd_status[256] = {
|
|
"Reserved",
|
|
"Command completed successfully",
|
|
"Reserved",
|
|
"Command completed successfully with ECC applied",
|
|
"Reserved",
|
|
"Command completed successfully with retries",
|
|
"Format Command partially completed", /* Status available */
|
|
"Command completed successfully with ECC and retries",
|
|
"Command completed with Warning", /* Command Error is available */
|
|
"Aborted",
|
|
"Reset completed",
|
|
"Data Transfer Ready", /* No Status Block available */
|
|
"Command terminated with failure", /* Device Error is available */
|
|
"DMA Error", /* Retry entire command as recovery */
|
|
"Command Block Error",
|
|
"Attention Error (Illegal Attention Code)",
|
|
/* 0x14 - 0xff reserved */
|
|
};
|
|
|
|
static const char * const edc_cmd_error[256] = {
|
|
"No Error",
|
|
"Invalid parameter in the command block",
|
|
"Reserved",
|
|
"Command not supported",
|
|
"Command Aborted per request",
|
|
"Reserved",
|
|
"Command rejected", /* Attachment diagnostic failure */
|
|
"Format Rejected", /* Prepare Format command is required */
|
|
"Format Error (Primary Map is not readable)",
|
|
"Format Error (Secondary map is not readable)",
|
|
"Format Error (Diagnostic Failure)",
|
|
"Format Warning (Secondary Map Overflow)",
|
|
"Reserved"
|
|
"Format Error (Host Checksum Error)",
|
|
"Reserved",
|
|
"Format Warning (Push table overflow)",
|
|
"Format Warning (More pushes than allowed)",
|
|
"Reserved",
|
|
"Format Warning (Error during verifying)",
|
|
"Invalid device number for the command",
|
|
/* 0x14-0xff reserved */
|
|
};
|
|
|
|
static const char * const edc_dev_errors[] = {
|
|
"No Error",
|
|
"Seek Fault", /* Device report */
|
|
"Interface Fault (Parity, Attn, or Cmd Complete Error)",
|
|
"Block not found (ID not found)",
|
|
"Block not found (AM not found)",
|
|
"Data ECC Error (hard error)",
|
|
"ID CRC Error",
|
|
"RBA Out of Range",
|
|
"Reserved",
|
|
"Defective Block",
|
|
"Reserved",
|
|
"Selection Error",
|
|
"Reserved",
|
|
"Write Fault",
|
|
"No index or sector pulse",
|
|
"Device Not Ready",
|
|
"Seek Error", /* Attachment report */
|
|
"Bad Format",
|
|
"Volume Overflow",
|
|
"No Data AM Found",
|
|
"Block not found (No ID AM or ID CRC error occurred)",
|
|
"Reserved",
|
|
"Reserved",
|
|
"No ID found on track (ID search)",
|
|
/* 0x19 - 0xff reserved */
|
|
};
|
|
|
|
static void
|
|
edc_dump_status_block(sc, devno, intr_id)
|
|
struct edc_mca_softc *sc;
|
|
int devno, intr_id;
|
|
{
|
|
struct ed_softc *ed = sc->sc_ed[devno];
|
|
printf("%s: Command: %s, Status: %s\n",
|
|
ed->sc_dev.dv_xname,
|
|
edc_commands[ed->sc_status_block[0] & 0x1f],
|
|
edc_cmd_status[SB_GET_CMD_STATUS(ed->sc_status_block)]
|
|
);
|
|
printf("%s: # left blocks: %u, last processed RBA: %u\n",
|
|
ed->sc_dev.dv_xname,
|
|
ed->sc_status_block[SB_RESBLKCNT_IDX],
|
|
(ed->sc_status_block[5] << 16) | ed->sc_status_block[4]);
|
|
|
|
if (intr_id == ISR_COMPLETED_WARNING) {
|
|
printf("%s: Command Error Code: %s\n",
|
|
ed->sc_dev.dv_xname,
|
|
edc_cmd_error[ed->sc_status_block[1] & 0xff]);
|
|
}
|
|
|
|
if (intr_id == ISR_CMD_FAILED) {
|
|
char buf[100];
|
|
|
|
printf("%s: Device Error Code: %s\n",
|
|
ed->sc_dev.dv_xname,
|
|
edc_dev_errors[ed->sc_status_block[2] & 0xff]);
|
|
bitmask_snprintf((ed->sc_status_block[2] & 0xff00) >> 8,
|
|
"\20"
|
|
"\01SeekOrCmdComplete"
|
|
"\02Track0Flag"
|
|
"\03WriteFault"
|
|
"\04Selected"
|
|
"\05Ready"
|
|
"\06Reserved0"
|
|
"\07STANDBY"
|
|
"\010Reserved0",
|
|
buf, sizeof(buf));
|
|
printf("%s: Device Status: %s\n",
|
|
ed->sc_dev.dv_xname, buf);
|
|
}
|
|
}
|