348 lines
12 KiB
C
348 lines
12 KiB
C
/* $NetBSD: dp83932reg.h,v 1.1 2001/07/05 14:37:41 thorpej Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_DP83932REG_H_
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#define _DEV_IC_DP83932REG_H_
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/*
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* Register description for the National Semiconductor DP83932
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* Systems-Oriented Network Interface Controller (SONIC).
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*/
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/*
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* SONIC Receive Descriptor Area.
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*/
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struct sonic_rda16 {
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uint16_t rda_status;
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uint16_t rda_bytecount;
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uint16_t rda_pkt_ptr0;
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uint16_t rda_pkt_ptr1;
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uint16_t rda_seqno;
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uint16_t rda_link;
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uint16_t rda_inuse;
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} __attribute__((__packed__));
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struct sonic_rda32 {
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uint32_t rda_status;
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uint32_t rda_bytecount;
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uint32_t rda_pkt_ptr0;
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uint32_t rda_pkt_ptr1;
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uint32_t rda_seqno;
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uint32_t rda_link;
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uint32_t rda_inuse;
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} __attribute__((__packed__));
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#define RDA_SEQNO_RBA(x) (((x) >> 8) & 0xff)
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#define RDA_SEQNO_RSN(x) ((x) & 0xff)
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#define RDA_LINK_EOL 0x01 /* end-of-list */
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/*
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* SONIC Receive Resource Area.
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*
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* Note, in 32-bit mode, Rx buffers must be aligned to 32-bit
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* boundaries, and in 16-bit mode, to 16-bit boundaries.
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*
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* Also note the `word count' is always in units of 16-bit words.
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*/
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struct sonic_rra16 {
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uint16_t rra_ptr0;
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uint16_t rra_ptr1;
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uint16_t rra_wc0;
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uint16_t rra_wc1;
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} __attribute__((__packed__));
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struct sonic_rra32 {
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uint32_t rra_ptr0;
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uint32_t rra_ptr1;
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uint32_t rra_wc0;
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uint32_t rra_wc1;
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} __attribute__((__packed__));
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/*
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* SONIC Transmit Descriptor Area
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*
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* Note the number of fragments defined here is arbitrary.
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*/
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#define SONIC_NTXFRAGS 8
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struct sonic_frag16 {
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uint16_t frag_ptr0;
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uint16_t frag_ptr1;
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uint16_t frag_size;
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} __attribute__((__packed__));
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struct sonic_frag32 {
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uint32_t frag_ptr0;
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uint32_t frag_ptr1;
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uint32_t frag_size;
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} __attribute__((__packed__));
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/*
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* Note the frag after the last frag is used to link up to the
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* next descriptor.
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*/
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struct sonic_tda16 {
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uint16_t tda_status;
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uint16_t tda_pktconfig;
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uint16_t tda_pktsize;
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uint16_t tda_fragcnt;
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struct sonic_frag16 tda_frags[SONIC_NTXFRAGS + 1];
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#if 0
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uint16_t tda_link;
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#endif
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} __attribute__((__packed__));
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struct sonic_tda32 {
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uint32_t tda_status;
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uint32_t tda_pktconfig;
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uint32_t tda_pktsize;
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uint32_t tda_fragcnt;
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struct sonic_frag32 tda_frags[SONIC_NTXFRAGS + 1];
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#if 0
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uint32_t tda_link;
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#endif
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} __attribute__((__packed__));
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#define TDA_STATUS_NCOL(x) (((x) >> 11) & 0x1f)
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#define TDA_LINK_EOL 0x01 /* end-of-list */
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/*
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* SONIC CAM Descriptor Area.
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*/
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struct sonic_cda16 {
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uint16_t cda_entry;
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uint16_t cda_addr0;
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uint16_t cda_addr1;
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uint16_t cda_addr2;
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} __attribute__((__packed__));
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struct sonic_cda32 {
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uint32_t cda_entry;
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uint32_t cda_addr0;
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uint32_t cda_addr1;
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uint32_t cda_addr2;
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} __attribute__((__packed__));
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/*
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* SONIC register file.
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*
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* NOTE: We define these as indices, and use a register map to deal
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* with different address strides.
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*/
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#define SONIC_CR 0x00 /* Command Register */
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#define CR_HTX (1U << 0) /* Halt Transmission */
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#define CR_TXP (1U << 1) /* Transmit Packets */
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#define CR_RXDIS (1U << 2) /* Receiver Disable */
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#define CR_RXEN (1U << 3) /* Receiver Enable */
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#define CR_STP (1U << 4) /* Stop Timer */
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#define CR_ST (1U << 5) /* Start Timer */
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#define CR_RST (1U << 7) /* Software Reset */
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#define CR_RRRA (1U << 8) /* Read RRA */
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#define CR_LCAM (1U << 9) /* Load CAM */
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#define SONIC_DCR 0x01 /* Data Configuration Register */
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#define DCR_TFT0 (1U << 0) /* Transmit FIFO Threshold (lo) */
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#define DCR_TFT1 (1U << 1) /* Transmit FIFO Threshold (hi) */
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#define DCR_RFT0 (1U << 2) /* Receive FIFO Threshold (lo) */
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#define DCR_RFT1 (1U << 3) /* Receive FIFO Threshold (hi) */
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#define DCR_BMS (1U << 4) /* Block Mode Select for DMA */
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#define DCR_DW (1U << 5) /* Data Width Select */
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#define DCR_WC0 (1U << 6) /* Wait State Control (lo) */
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#define DCR_WC1 (1U << 7) /* Wait State Control (hi) */
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#define DCR_USR0 (1U << 8) /* User Definable Pin 0 */
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#define DCR_USR1 (1U << 9) /* User Definable Pin 1 */
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#define DCR_SBUS (1U << 10) /* Synchronous Bus Mode */
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#define DCR_PO0 (1U << 11) /* Programmable Output 0 */
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#define DCR_PO1 (1U << 12) /* Programmable Output 1 */
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#define DCR_LBR (1U << 13) /* Latched Bus Retry */
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#define DCR_EXBUS (1U << 15) /* Extended Bus Mode */
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#define SONIC_RCR 0x02 /* Receive Control Register */
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#define RCR_PRX (1U << 0) /* Packet Received OK */
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#define RCR_LBK (1U << 1) /* Loopback Packet Received */
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#define RCR_FAER (1U << 2) /* Frame Alignment Error */
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#define RCR_CRCR (1U << 3) /* CRC Error */
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#define RCR_COL (1U << 4) /* Collision Activity */
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#define RCR_CRS (1U << 5) /* Carrier Sense Activity */
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#define RCR_LPKT (1U << 6) /* Last Packet in RBA */
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#define RCR_BC (1U << 7) /* Broadcast Packet Received */
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#define RCR_MC (1U << 8) /* Multicast Packet Received */
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#define RCR_LB0 (1U << 9) /* Loopback Control 0 */
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#define RCR_LB1 (1U << 10) /* Loopback Control 1 */
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#define RCR_AMC (1U << 11) /* Accept All Multicast Packets */
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#define RCR_PRO (1U << 12) /* Physical Promiscuous Packets */
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#define RCR_BRD (1U << 13) /* Accept Broadcast Packets */
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#define RCR_RNT (1U << 14) /* Accept Runt Packets */
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#define RCR_ERR (1U << 15) /* Accept Packets with Errors */
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#define SONIC_TCR 0x03 /* Transmit Control Register */
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#define TCR_PTX (1U << 0) /* Packet Transmitted OK */
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#define TCR_BCM (1U << 1) /* Byte Count Mismatch */
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#define TCR_FU (1U << 2) /* FIFO Underrun */
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#define TCR_PMB (1U << 3) /* Packet Monitored Bad */
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#define TCR_OWC (1U << 5) /* Out of Window Collision */
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#define TCR_EXC (1U << 6) /* Excessive Collisions */
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#define TCR_CRSL (1U << 7) /* Carrier Sense Lost */
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#define TCR_NCRS (1U << 8) /* No Carrier Sense */
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#define TCR_DEF (1U << 9) /* Deferred Transmission */
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#define TCR_EXD (1U << 10) /* Excessive Deferral */
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#define TCR_EXDIS (1U << 12) /* Disable Excessive Deferral Timer */
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#define TCR_CRCI (1U << 13) /* CRC Inhibit */
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#define TCR_POWC (1U << 14) /* Programmed Out of Window Col. Tmr */
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#define TCR_PINT (1U << 15) /* Programmable Interrupt */
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#define SONIC_IMR 0x04 /* Interrupt Mask Register */
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#define IMR_RFO (1U << 0) /* Rx FIFO Overrun */
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#define IMR_MP (1U << 1) /* Missed Packet Tally */
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#define IMR_FAE (1U << 2) /* Frame Alignment Error Tally */
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#define IMR_CRC (1U << 3) /* CRC Tally */
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#define IMR_RBA (1U << 4) /* RBA Exceeded */
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#define IMR_RBE (1U << 5) /* Rx Buffers Exhausted */
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#define IMR_RDE (1U << 6) /* Rx Descriptors Exhausted */
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#define IMR_TC (1U << 7) /* Timer Complete */
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#define IMR_TXER (1U << 8) /* Transmit Error */
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#define IMR_PTX (1U << 9) /* Transmit OK */
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#define IMR_PRX (1U << 10) /* Packet Received */
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#define IMR_PINT (1U << 11) /* Programmable Interrupt */
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#define IMR_LCD (1U << 12) /* Load CAM Done */
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#define IMR_HBL (1U << 13) /* Heartbeat Lost */
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#define IMR_BR (1U << 14) /* Bus Retry Occurred */
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#define SONIC_ISR 0x05 /* Interrupt Status Register */
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/* See IMR bits. */
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#define SONIC_UTDAR 0x06 /* Upper Tx Descriptor Adress Register */
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#define SONIC_CTDAR 0x07 /* Current Tx Descriptor Address Register */
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#define SONIC_TPS 0x08 /* Transmit Packet Size */
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#define SONIC_TFC 0x09 /* Transmit Fragment Count */
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#define SONIC_TSA0 0x0a /* Transmit Start Address (lo) */
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#define SONIC_TSA1 0x0b /* Transmit Start Address (hi) */
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#define SONIC_TFS 0x0c /* Transmit Fragment Size */
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#define SONIC_URDAR 0x0d /* Upper Rx Descriptor Address Register */
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#define SONIC_CRDAR 0x0e /* Current Rx Descriptor Address Register */
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#define SONIC_CRBA0 0x0f /* Current Receive Buffer Address (lo) */
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#define SONIC_CRBA1 0x10 /* Current Receive Buffer Address (hi) */
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#define SONIC_RBWC0 0x11 /* Remaining Buffer Word Count 0 */
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#define SONIC_RBWC1 0x12 /* Remaining Buffer Word Count 1 */
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#define SONIC_EOBC 0x13 /* End Of Buffer Word Count */
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#define SONIC_URRAR 0x14 /* Upper Rx Resource Address Register */
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#define SONIC_RSAR 0x15 /* Resource Start Address Register */
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#define SONIC_REAR 0x16 /* Resource End Address Register */
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#define SONIC_RRR 0x17 /* Resource Read Register */
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#define SONIC_RWR 0x18 /* Resource Write Register */
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#define SONIC_TRBA0 0x19 /* Temporary Receive Buffer Address (lo) */
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#define SONIC_TRBA1 0x1a /* Temporary Receive Buffer Address (hi) */
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#define SONIC_TBWC0 0x1b /* Temporary Buffer Word Count 0 */
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#define SONIC_TBWC1 0x1c /* Temporary Buffer Word Count 1 */
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#define SONIC_ADDR0 0x1d /* Address Generator 0 */
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#define SONIC_ADDR1 0x1e /* Address Generator 1 */
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#define SONIC_LLFA 0x1f /* Last Link Field Address */
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#define SONIC_TTDA 0x20 /* Temporary Tx Descriptor Address */
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#define SONIC_CEP 0x21 /* CAM Entry Pointer */
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#define SONIC_CAP2 0x22 /* CAM Address Port 2 */
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#define SONIC_CAP1 0x23 /* CAM Address Port 1 */
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#define SONIC_CAP0 0x24 /* CAM Address Port 0 */
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#define SONIC_CER 0x25 /* CAM Enable Register */
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#define SONIC_CDP 0x26 /* CAM Descriptor Pointer */
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#define SONIC_CDC 0x27 /* CAM Descriptor Count */
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#define SONIC_SRR 0x28 /* Silicon Revision Register */
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#define SONIC_WT0 0x29 /* Watchdog Timer 0 */
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#define SONIC_WT1 0x2a /* Watchdog Timer 1 */
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#define SONIC_RSC 0x2b /* Receive Sequence Counter */
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#define SONIC_CRCETC 0x2c /* CRC Error Tally Count */
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#define SONIC_FAET 0x2d /* Frame Alignment Error Tally */
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#define SONIC_MPT 0x2e /* Missed Packet Tally */
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#define SONIC_DCR2 0x3f /* Data Configuration Register 2 */
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#define DCR2_RJCM (1U << 0) /* Reject on CAM Match */
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#define DCR2_PCNM (1U << 1) /* Packet Compress When not Matched */
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#define DCR2_PCM (1U << 2) /* Packet Compress When Matched */
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#define DCR2_PH (1U << 4) /* Program Hold */
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#define DCR2_EXPO0 (1U << 12) /* Extended Programmable Output 0 */
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#define DCR2_EXPO1 (1U << 13) /* Extended Programmable Output 1 */
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#define DCR2_EXPO2 (1U << 14) /* Extended Programmable Output 2 */
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#define DCR2_EXPO3 (1U << 15) /* Extended Programmable Output 3 */
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#define SONIC_NREGS 0x40
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#endif /* _DEV_IC_DP83932REG_H_ */
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