113 lines
3.7 KiB
C
113 lines
3.7 KiB
C
/* $NetBSD: tc_machdep.h,v 1.4 2000/06/01 00:04:50 cgd Exp $ */
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/*
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* Copyright (c) 1994, 1995 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Machine-specific definitions for TurboChannel support.
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*
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* This file must typedef the following types:
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*
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* tc_addr_t TurboChannel bus address
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* tc_offset_t TurboChannel bus address difference (offset)
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*
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* This file must prototype or define the following functions
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* or macros (one or more of which may be no-ops):
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*
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* tc_mb() read/write memory barrier (any CPU<->memory
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* reads/writes before must complete before any
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* CPU<->memory reads/writes after).
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* tc_wmb() write memory barrier (any CPU<->memory writes
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* before must complete before any CPU<->memory
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* writes after).
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* tc_syncbus() sync TC bus; make sure CPU writes are
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* propagated across the TurboChannel bus.
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* tc_badaddr() return non-zero if the given address is invalid.
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* TC_DENSE_TO_SPARSE()
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* convert the given physical address in
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* TurboChannel dense space to the corresponding
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* address in TurboChannel sparse space.
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* TC_PHYS_TO_UNCACHED()
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* convert the given system memory physical address
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* to the physical address of the corresponding
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* region that is not cached.
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*/
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typedef u_int64_t tc_addr_t;
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typedef int32_t tc_offset_t;
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#define tc_mb() alpha_mb()
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#define tc_wmb() alpha_wmb()
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/*
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* A junk address to read from, to make sure writes are complete. See
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* System Programmer's Manual, section 9.3 (p. 9-4), and sacrifice a
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* chicken.
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*/
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#define tc_syncbus() \
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do { \
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volatile u_int32_t no_optimize; \
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no_optimize = \
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*(volatile u_int32_t *)ALPHA_PHYS_TO_K0SEG(0x00000001f0080220); \
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} while (0)
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#define tc_badaddr(tcaddr) \
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badaddr((void *)(tcaddr), sizeof (u_int32_t))
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#define TC_SPACE_IND 0xffffffffe0000003
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#define TC_SPACE_DENSE 0x0000000000000000
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#define TC_SPACE_DENSE_OFFSET 0x0000000007fffffc
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#define TC_SPACE_SPARSE 0x0000000010000000
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#define TC_SPACE_SPARSE_OFFSET 0x000000000ffffff8
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#define TC_DENSE_TO_SPARSE(addr) \
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(((addr) & TC_SPACE_IND) | TC_SPACE_SPARSE | \
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(((addr) & TC_SPACE_DENSE_OFFSET) << 1))
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#define TC_PHYS_TO_UNCACHED(addr) \
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(addr)
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/*
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* These functions are private, and may not be called by
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* machine-independent code.
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*/
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bus_space_tag_t tc_bus_mem_init(void *memv);
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void tc_dma_init(void);
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/*
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* Address of scatter/gather SRAM on the 3000/500-series.
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*
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* There is room for 32K entries, yielding 256M of sgva space.
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* The page table is readable in both dense and sparse space.
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* The page table is writable only in sparse space.
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*
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* In sparse space, the 32-bit PTEs are followed by 32-bits
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* of pad.
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*/
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#define TC_SGSRAM_DENSE 0x0000001c2800000UL
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#define TC_SGSRAM_SPARSE 0x0000001d5000000UL
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