281 lines
7.7 KiB
C
281 lines
7.7 KiB
C
/* $NetBSD: cpc700.c,v 1.8 2004/08/30 15:05:19 drochner Exp $ */
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/*
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* The IBM CPC700 is a bridge chip for the PowerPC. It contains
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* - CPU interface
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* - DRAM controller
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* - PCI bus master & slave controller
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* - interrupt controller
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* - timer
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* - two UARTs
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* - two IIC ports
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*
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* This driver handles the overall device and enumeration of the
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* supported subdevices. NetBSD knows how to handle:
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* - PCI master
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* - interrupt controller
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* - UARTs
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* Skeleton drivers are provided for the timer and IIC.
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*
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* XXX This driver assumes that there is only one instance of it.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpc700.c,v 1.8 2004/08/30 15:05:19 drochner Exp $");
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#include "pci.h"
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#include "opt_pci.h"
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#include <sys/param.h>
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#include <sys/extent.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/systm.h>
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#include <machine/bus.h>
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#include "locators.h"
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pciconf.h>
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#include <dev/ic/cpc700reg.h>
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#include <dev/ic/cpc700var.h>
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#include <dev/ic/cpc700uic.h>
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union attach_args {
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struct pcibus_attach_args pba;
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struct cpcbus_attach_args cba;
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};
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void
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cpc_attach(struct device *self, pci_chipset_tag_t pc, bus_space_tag_t mem,
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bus_space_tag_t pciio, bus_dma_tag_t tag, int attachpci,
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uint freq);
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static bus_space_tag_t the_cpc_tag;
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static bus_space_handle_t the_cpc_handle;
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#define INL(a) bus_space_read_stream_4(the_cpc_tag, the_cpc_handle, (a))
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#define OUTL(a, d) bus_space_write_stream_4(the_cpc_tag, the_cpc_handle, (a), d)
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static int
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cpc_print(void *aux, const char *pnp)
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{
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struct cpcbus_attach_args *caa = aux;
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if (pnp)
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aprint_normal("%s at %s", caa->cpca_name, pnp);
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aprint_normal(" addr 0x%08x", caa->cpca_addr);
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if (caa->cpca_irq != CPCBUSCF_IRQ_DEFAULT)
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aprint_normal(" irq %d", caa->cpca_irq);
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return (UNCONF);
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}
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static int
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cpc_submatch(struct device *parent, struct cfdata *cf,
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const locdesc_t *ldesc, void *aux)
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{
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struct cpcbus_attach_args *caa = aux;
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if (cf->cf_loc[CPCBUSCF_ADDR] != caa->cpca_addr)
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return (0);
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return (config_match(parent, cf, aux));
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}
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/*
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* Attach the cpc.
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*/
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void
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cpc_attach(struct device *self, pci_chipset_tag_t pc, bus_space_tag_t mem,
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bus_space_tag_t pciio, bus_dma_tag_t dma, int attachpci,
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uint freq)
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{
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union attach_args aa;
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int i;
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pcitag_t tag;
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pcireg_t erren;
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pcireg_t v;
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static struct {
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const char *name;
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bus_addr_t addr;
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int irq;
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} devs[] = {
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{ "com", CPC_COM0, CPC_IB_UART_0 },
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{ "com", CPC_COM1, CPC_IB_UART_1 },
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{ "cpctim", CPC_TIMER, CPCBUSCF_IRQ_DEFAULT },
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{ "cpciic", CPC_IIC0, CPC_IB_IIC_0 },
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{ "cpciic", CPC_IIC1, CPC_IB_IIC_1 },
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{ NULL, 0 }
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};
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#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
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struct extent *ioext, *memext;
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#ifdef PCI_CONFIGURE_VERBOSE
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extern int pci_conf_debug;
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pci_conf_debug = 1;
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#endif
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#endif
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printf(": IBM CPC700\n");
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the_cpc_tag = mem;
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if (bus_space_map(mem, CPC_UIC_BASE, CPC_UIC_SIZE, 0,
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&the_cpc_handle)) {
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printf("%s: can't map i/o space\n", self->dv_xname);
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return;
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}
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aa.cba.cpca_tag = mem;
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aa.cba.cpca_freq = freq;
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for (i = 0; devs[i].name; i++) {
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aa.cba.cpca_name = devs[i].name;
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aa.cba.cpca_addr = devs[i].addr;
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aa.cba.cpca_irq = devs[i].irq;
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config_found_sm_loc(self, "cpcbus", NULL, &aa.cba,
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cpc_print, cpc_submatch);
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}
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tag = pci_make_tag(pc, 0, 0, 0);
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aa.pba.pba_iot = pciio;
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aa.pba.pba_memt = mem;
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aa.pba.pba_dmat = dma;
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aa.pba.pba_pc = 0;
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aa.pba.pba_flags = PCI_FLAGS_MEM_ENABLED | PCI_FLAGS_IO_ENABLED;
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aa.pba.pba_bus = 0;
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/* Save PCI error condition reg. */
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erren = pci_conf_read(pc, tag, CPC_PCI_BRDGERR);
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/* Don't generate errors during probe. */
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pci_conf_write(pc, tag, CPC_PCI_BRDGERR, 0);
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/* Program MITL */
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v = pci_conf_read(pc, tag, CPC_BRIDGE_OPTIONS2);
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v &= ~(CPC_BRIDGE_O2_ILAT_MASK | CPC_BRIDGE_O2_SLAT_MASK);
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v |= (CPC_BRIDGE_O2_ILAT_PRIM_ASYNC << CPC_BRIDGE_O2_ILAT_SHIFT) |
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(CPC_BRIDGE_O2_2LAT_PRIM_ASYNC << CPC_BRIDGE_O2_SLAT_SHIFT);
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pci_conf_write(pc, tag, CPC_BRIDGE_OPTIONS2, v);
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#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
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ioext = extent_create("pciio", CPC_PCI_IO_START, CPC_PCI_IO_END,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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memext = extent_create("pcimem", CPC_PCI_MEM_BASE, CPC_PCI_MEM_END,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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pci_configure_bus(0, ioext, memext, NULL, 0, 32);
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extent_destroy(ioext);
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extent_destroy(memext);
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#endif
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config_found_ia(self, "pcibus", &aa.pba, pcibusprint);
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/* Restore error triggers, and clear errors */
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pci_conf_write(pc, tag, CPC_PCI_BRDGERR, erren | CPC_PCI_CLEARERR);
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}
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/***************************************************************************/
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/*
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* Interrupt controller.
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*/
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void
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cpc700_init_intr(bus_space_tag_t bt, bus_space_handle_t bh,
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u_int32_t active, u_int32_t level)
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{
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/* XXX */
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the_cpc_tag = bt;
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the_cpc_handle = bh;
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/*
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* See CPC700 manual for information about what
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* interrupts have which properties.
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*/
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OUTL(CPC_UIC_SR, 0xffffffff); /* clear all intrs */
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OUTL(CPC_UIC_ER, 0x00000000); /* disable all intrs */
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OUTL(CPC_UIC_CR, 0xffffffff); /* gen INT not MCP */
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OUTL(CPC_UIC_PR, 0xffff8000 | active); /* 0 = active low */
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OUTL(CPC_UIC_TR, 0xc0000000 | level); /* 0 = level intr */
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OUTL(CPC_UIC_VR, CPC_UIC_CVR_PRI); /* intr 0 is highest */
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}
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int
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cpc700_read_irq(void)
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{
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int irq;
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u_int32_t irqs;
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irqs = INL(CPC_UIC_MSR);
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for (irq = 0; irq < ICU_LEN; irq++) {
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if (irqs & CPC_INTR_MASK(irq))
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return (irq);
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}
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return (-1);
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}
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void
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cpc700_eoi(int irq)
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{
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OUTL(CPC_UIC_SR, CPC_INTR_MASK(irq));
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}
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void
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cpc700_disable_irq(int irq)
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{
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u_int32_t reg;
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reg = INL(CPC_UIC_ER);
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reg &= ~CPC_INTR_MASK(irq);
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OUTL(CPC_UIC_ER, reg);
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}
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void
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cpc700_enable_irq(int irq)
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{
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u_int32_t reg;
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reg = INL(CPC_UIC_ER);
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reg |= CPC_INTR_MASK(irq);
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OUTL(CPC_UIC_ER, reg);
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}
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