458 lines
12 KiB
C
458 lines
12 KiB
C
/* $NetBSD: extintr.c,v 1.11 2002/03/04 02:19:08 simonb Exp $ */
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/* $OpenBSD: isabus.c,v 1.12 1999/06/15 02:40:05 rahnds Exp $ */
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/*-
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* Copyright (c) 1995 Per Fogelstrom
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* Copyright (c) 1993, 1994 Charles Hannum.
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz and Don Ahn.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)isa.c 7.2 (Berkeley) 5/12/91
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*/
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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/*
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Copyright 1988, 1989 by Intel Corporation, Santa Clara, California.
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All Rights Reserved
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Permission to use, copy, modify, and distribute this software and
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its documentation for any purpose and without fee is hereby
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granted, provided that the above copyright notice appears in all
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copies and that both the copyright notice and this permission notice
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appear in supporting documentation, and that the name of Intel
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not be used in advertising or publicity pertaining to distribution
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of the software without specific, written prior permission.
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INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
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INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
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IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
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CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
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NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
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WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <machine/intr.h>
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#include <machine/psl.h>
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#include <dev/isa/isavar.h>
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void intr_calculatemasks(void);
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int fakeintr(void *);
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void ext_intr(void);
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int imen = 0xffffffff;
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volatile int cpl, ipending, astpending, tickspending;
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int imask[NIPL];
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int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN];
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struct intrhand *intrhand[ICU_LEN];
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unsigned intrcnt2[ICU_LEN];
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int
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fakeintr(void *arg)
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{
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return 0;
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}
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/*
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* Process an interrupt from the ISA bus.
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* When we get here remember we have "delayed" ipl mask
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* settings from the spl<foo>() calls. Yes it's faster
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* to do it like this because SPL's are done so frequently
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* and interrupts are likely to *NOT* happen most of the
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* times the spl level is changed.
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*/
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void
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ext_intr(void)
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{
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u_int8_t irq;
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int r_imen;
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int pcpl;
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struct intrhand *ih;
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/* what about enabling external interrupt in here? */
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pcpl = splhigh(); /* Turn off all */
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irq = isa_intr();
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intrcnt2[irq]++;
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r_imen = 1 << irq;
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if ((pcpl & r_imen) != 0) {
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ipending |= r_imen; /* Masked! Mark this as pending */
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imen |= r_imen;
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isa_intr_mask(imen);
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} else {
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ih = intrhand[irq];
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if (ih == NULL)
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printf("spurious interrupt %d\n", irq);
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while (ih) {
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(*ih->ih_fun)(ih->ih_arg);
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ih = ih->ih_next;
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}
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isa_intr_clr(irq);
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uvmexp.intrs++;
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intrcnt[irq]++;
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}
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splx(pcpl); /* Process pendings. */
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}
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/*
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* Same as the above, but using the board's interrupt vector register.
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*/
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void
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ext_intr_ivr(void)
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{
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u_int8_t irq;
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int r_imen;
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int pcpl;
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struct intrhand *ih;
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/* what about enabling external interrupt in here? */
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pcpl = splhigh(); /* Turn off all */
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irq = *((u_char *)prep_intr_reg + INTR_VECTOR_REG);
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intrcnt2[irq]++;
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r_imen = 1 << irq;
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if ((pcpl & r_imen) != 0) {
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ipending |= r_imen; /* Masked! Mark this as pending */
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imen |= r_imen;
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isa_intr_mask(imen);
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} else {
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ih = intrhand[irq];
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if (ih == NULL)
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printf("spurious interrupt %d\n", irq);
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while (ih) {
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(*ih->ih_fun)(ih->ih_arg);
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ih = ih->ih_next;
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}
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isa_intr_clr(irq);
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uvmexp.intrs++;
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intrcnt[irq]++;
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}
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splx(pcpl); /* Process pendings. */
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}
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void *
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intr_establish(int irq, int type, int level, int (*ih_fun)(void *), void *ih_arg)
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{
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struct intrhand **p, *q, *ih;
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static struct intrhand fakehand = {fakeintr};
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/* no point in sleeping unless someone can free memory. */
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ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
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if (ih == NULL)
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panic("intr_establish: can't malloc handler info");
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if (!LEGAL_IRQ(irq) || type == IST_NONE)
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panic("intr_establish: bogus irq or type");
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switch (intrtype[irq]) {
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case IST_NONE:
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intrtype[irq] = type;
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break;
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case IST_LEVEL:
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case IST_EDGE:
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if (type == intrtype[irq])
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break;
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case IST_PULSE:
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if (type != IST_NONE)
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panic("intr_establish: can't share %s with %s irq %d",
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isa_intr_typename(intrtype[irq]),
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isa_intr_typename(type), irq);
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break;
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}
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/*
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* Figure out where to put the handler.
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* This is O(N^2), but we want to preserve the order, and N is
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* generally small.
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*/
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for (p = &intrhand[irq]; (q = *p) != NULL; p = &q->ih_next)
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continue;
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/*
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* Actually install a fake handler momentarily, since we might be doing
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* this with interrupts enabled and don't want the real routine called
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* until masking is set up.
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*/
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fakehand.ih_level = level;
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*p = &fakehand;
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intr_calculatemasks();
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/*
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* Poke the real handler in now.
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*/
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ih->ih_fun = ih_fun;
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ih->ih_arg = ih_arg;
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ih->ih_count = 0;
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ih->ih_next = NULL;
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ih->ih_level = level;
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ih->ih_irq = irq;
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*p = ih;
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isa_setirqstat(irq, 1, type);
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return (ih);
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}
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void
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intr_disestablish(void *arg)
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{
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struct intrhand *ih = arg;
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int irq = ih->ih_irq;
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struct intrhand **p, *q;
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if (!LEGAL_IRQ(irq))
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panic("intr_disestablish: bogus irq");
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/*
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* Remove the handler from the chain.
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* This is O(n^2), too.
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*/
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for (p = &intrhand[irq]; (q = *p) != NULL && q != ih; p = &q->ih_next)
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;
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if (q)
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*p = q->ih_next;
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else
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panic("intr_disestablish: handler not registered");
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free((void *)ih, M_DEVBUF);
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intr_calculatemasks();
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if (intrhand[irq] == NULL)
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intrtype[irq] = IST_NONE;
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}
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/*
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* Recalculate the interrupt masks from scratch.
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* We could code special registry and deregistry versions of this function that
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* would be faster, but the code would be nastier, and we don't expect this to
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* happen very much anyway.
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*/
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void
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intr_calculatemasks(void)
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{
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int irq, level;
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struct intrhand *q;
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/* First, figure out which levels each IRQ uses. */
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for (irq = 0; irq < ICU_LEN; irq++) {
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register int levels = 0;
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for (q = intrhand[irq]; q; q = q->ih_next)
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levels |= 1 << q->ih_level;
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intrlevel[irq] = levels;
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}
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/* Then figure out which IRQs use each level. */
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for (level = 0; level < NIPL; level++) {
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register int irqs = 0;
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for (irq = 0; irq < ICU_LEN; irq++)
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if (intrlevel[irq] & (1 << level))
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irqs |= 1 << irq;
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imask[level] = irqs;
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}
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/*
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* Initialize the soft interrupt masks to block themselves.
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*/
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imask[IPL_SOFTCLOCK] = SINT_CLOCK;
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imask[IPL_SOFTNET] = SINT_NET;
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imask[IPL_SOFTSERIAL] = SINT_SERIAL;
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/*
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* IPL_NONE is used for hardware interrupts that are never blocked,
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* and do not block anything else.
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*/
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imask[IPL_NONE] = 0;
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/*
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* Enforce a hierarchy that gives slow devices a better chance at not
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* dropping data.
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*/
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imask[IPL_SOFTCLOCK] |= imask[IPL_NONE];
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imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK];
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imask[IPL_BIO] |= imask[IPL_SOFTNET];
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imask[IPL_NET] |= imask[IPL_BIO];
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imask[IPL_SOFTSERIAL] |= imask[IPL_NET];
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imask[IPL_TTY] |= imask[IPL_SOFTSERIAL];
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/*
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* There are tty, network and disk drivers that use free() at interrupt
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* time, so imp > (tty | net | bio).
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*/
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imask[IPL_IMP] |= imask[IPL_TTY];
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imask[IPL_AUDIO] |= imask[IPL_IMP];
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/*
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* Since run queues may be manipulated by both the statclock and tty,
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* network, and disk drivers, clock > imp.
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*/
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imask[IPL_CLOCK] |= SPL_CLOCK; /* block the clock */
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imask[IPL_CLOCK] |= imask[IPL_AUDIO];
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/*
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* IPL_HIGH must block everything that can manipulate a run queue.
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*/
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imask[IPL_HIGH] |= imask[IPL_CLOCK];
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/*
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* We need serial drivers to run at the absolute highest priority to
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* avoid overruns, so serial > high.
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*/
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imask[IPL_SERIAL] |= imask[IPL_HIGH];
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/* And eventually calculate the complete masks. */
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for (irq = 0; irq < ICU_LEN; irq++) {
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register int irqs = 1 << irq;
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for (q = intrhand[irq]; q; q = q->ih_next)
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irqs |= imask[q->ih_level];
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intrmask[irq] = irqs;
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}
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{
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register int irqs = 0;
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for (irq = 0; irq < ICU_LEN; irq++)
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if (intrhand[irq])
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irqs |= 1 << irq;
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if (irqs >= 0x100) /* any IRQs >= 8 in use */
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irqs |= 1 << IRQ_SLAVE;
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imen = ~irqs;
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isa_intr_mask(imen);
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}
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}
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void
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do_pending_int(void)
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{
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struct intrhand *ih;
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int irq;
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int pcpl;
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int hwpend;
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int emsr, dmsr;
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static int processing;
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if (processing)
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return;
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processing = 1;
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asm volatile("mfmsr %0" : "=r"(emsr));
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dmsr = emsr & ~PSL_EE;
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asm volatile("mtmsr %0" :: "r"(dmsr));
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pcpl = splhigh(); /* Turn off all */
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hwpend = ipending & ~pcpl; /* Do now unmasked pendings */
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imen &= ~hwpend;
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hwpend &= ~SINT_MASK;
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while (hwpend) {
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irq = ffs(hwpend) - 1;
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hwpend &= ~(1L << irq);
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ih = intrhand[irq];
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while (ih) {
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(*ih->ih_fun)(ih->ih_arg);
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ih = ih->ih_next;
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}
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isa_intr_clr(irq);
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uvmexp.intrs++;
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intrcnt[irq]++;
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}
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if ((ipending & ~pcpl) & SINT_CLOCK) {
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ipending &= ~SINT_CLOCK;
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softclock(NULL);
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}
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if ((ipending & ~pcpl) & SINT_NET) {
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ipending &= ~SINT_NET;
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softnet();
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}
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if ((ipending & ~pcpl) & SINT_SERIAL) {
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ipending &= ~SINT_SERIAL;
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softserial();
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}
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ipending &= pcpl;
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cpl = pcpl; /* Don't use splx... we are here already! */
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isa_intr_mask(imen);
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asm volatile("mtmsr %0" :: "r"(emsr));
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processing = 0;
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}
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