nisimura f4b74d3898 - Reimplement MIPS1 cache size dectection logic taking advantage of the
fact the direct mapped cache makes address alias effect.
- Just turn on processor master interrupt mask IEc (SR_INT_IE) bit prior
  to call syscall() kernel entry point.  IEp is always 1 in this case
  by defition.
2000-09-16 04:54:44 +00:00
2000-09-14 20:36:39 +00:00
2000-09-14 01:24:31 +00:00
2000-09-14 16:02:24 +00:00
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