NetBSD/sys/arch/mips/include/cache_r10k.h
shin 70f5a0a5b2 cache_r10k.c rev. 1.1 is broken. Because,
1) R10k uses VA0 to select cache ways, but in rev. 1.1, VA14
	   is used instead.
	2) R10k does not support HitWriteBack and should map HitWriteBack
	   to HitWriteBackInvalidate, but in rev. 1.1, HitWriteBack is not
	   handled properly.

So, cache_r10k.c rev. 1.1 was replaced by new implementation.
2003-11-01 04:42:56 +00:00

88 lines
4.0 KiB
C

/* $NetBSD: cache_r10k.h,v 1.2 2003/11/01 04:42:56 shin Exp $ */
/*
* Copyright (c) 2003 KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Cache definitions/operations for R10000-style caches.
*/
#define CACHEOP_R10K_CBARRIER (5 << 2) /* I */
#define CACHEOP_R10K_IDX_LOAD_DATA (6 << 2) /* I, D, SD */
#define CACHEOP_R10K_IDX_STORE_DATA (7 << 2) /* SI, SD */
#if defined(_KERNEL) && !defined(_LOCORE)
void r10k_icache_sync_all(void);
void r10k_icache_sync_range(vaddr_t, vsize_t);
void r10k_icache_sync_range_index(vaddr_t, vsize_t);
void r10k_pdcache_wbinv_all(void);
void r10k_pdcache_wbinv_range(vaddr_t, vsize_t);
void r10k_pdcache_wbinv_range_index(vaddr_t, vsize_t);
void r10k_pdcache_inv_range(vaddr_t, vsize_t);
void r10k_pdcache_wb_range(vaddr_t, vsize_t);
void r10k_sdcache_wbinv_all(void);
void r10k_sdcache_wbinv_range(vaddr_t, vsize_t);
void r10k_sdcache_wbinv_range_index(vaddr_t, vsize_t);
void r10k_sdcache_inv_range(vaddr_t, vsize_t);
void r10k_sdcache_wb_range(vaddr_t, vsize_t);
#endif /* _KERNEL && !_LOCORE */