320 lines
9.0 KiB
C
320 lines
9.0 KiB
C
/* $NetBSD: gt_mainbus.c,v 1.4 2011/07/01 20:51:15 dyoung Exp $ */
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/*
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* Copyright (c) 2010 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gt_mainbus.c,v 1.4 2011/07/01 20:51:15 dyoung Exp $");
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#include "opt_pci.h"
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#include "opt_marvell.h"
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#include "gtpci.h"
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#include "pci.h"
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#include "isa.h"
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#define _POWERPC_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <machine/autoconf.h>
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#include <sys/bus.h>
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#include <machine/isa_machdep.h>
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#include <machine/pegasosreg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciconf.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/marvell/gtreg.h>
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#include <dev/marvell/gtvar.h>
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#include <dev/marvell/gtpcireg.h>
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#include <dev/marvell/gtpcivar.h>
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#include <dev/marvell/marvellvar.h>
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#include <dev/ofw/openfirm.h>
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static int gt_match(device_t, cfdata_t, void *);
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static void gt_attach(device_t, device_t, void *);
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#if NGTPCI > 0
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static void gtpci_md_attach_hook(device_t, device_t,
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struct pcibus_attach_args *);
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void gtpci_md_conf_interrupt(void *, int, int, int, int, int *);
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int gtpci_md_conf_hook(void *, int, int, int, pcireg_t);
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#endif
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CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc), gt_match, gt_attach, NULL, NULL);
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static struct powerpc_bus_space pegasosii_gt_bs_tag = {
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.pbs_offset = PEGASOS2_GT_REGBASE,
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.pbs_base = 0x00000000,
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.pbs_limit = GT_SIZE,
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};
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static char ex_storage[EXTENT_FIXED_STORAGE_SIZE(8)]
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__attribute__((aligned(8)));
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struct powerpc_bus_dma_tag pegasosii_bus_dma_tag = {
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0, /* _bounce_thresh */
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_bus_dmamap_create,
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_bus_dmamap_destroy,
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_bus_dmamap_load,
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_bus_dmamap_load_mbuf,
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_bus_dmamap_load_uio,
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_bus_dmamap_load_raw,
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_bus_dmamap_unload,
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_bus_dmamap_sync,
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_bus_dmamem_alloc,
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_bus_dmamem_free,
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_bus_dmamem_map,
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_bus_dmamem_unmap,
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_bus_dmamem_mmap,
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};
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#if NGTPCI > 0
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struct powerpc_bus_space
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gtpci0_io_bs_tag, gtpci0_mem_bs_tag,
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gtpci1_io_bs_tag, gtpci1_mem_bs_tag;
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#endif
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struct gtpci_prot gtpci0_prot = {
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GTPCI_ACBL_RDSIZE_32BYTE |
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GTPCI_ACBL_RDMBURST_32BYTE |
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GTPCI_ACBL_PCISWAP_BYTESWAP |
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GTPCI_ACBL_SNOOP_WB |
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GTPCI_ACBL_EN,
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0,
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}, gtpci1_prot = {
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GTPCI_ACBL_RDSIZE_128BYTE |
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GTPCI_ACBL_RDMBURST_32BYTE |
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GTPCI_ACBL_PCISWAP_BYTESWAP |
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GTPCI_ACBL_SNOOP_WB |
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GTPCI_ACBL_EN,
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0,
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};
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int
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gt_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct confargs *ca = aux;
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uint32_t device_id, vendor_id;
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int node;
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char name[32];
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if (strcmp(ca->ca_name, "gt") != 0 ||
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strcmp(model_name, "Pegasos2") != 0)
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return 0;
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/* Paranoid check... */
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for (node = OF_child(OF_finddevice("/")); node; node = OF_peer(node)) {
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memset(name, 0, sizeof(name));
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if (OF_getprop(node, "name", name, sizeof(name)) == -1)
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continue;
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if (strcmp(name, "pci") == 0) {
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for (node = OF_child(node); node;
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node = OF_peer(node)) {
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if (OF_getprop(node, "vendor-id",
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&vendor_id, sizeof(vendor_id)) == -1)
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continue;
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if (OF_getprop(node, "device-id",
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&device_id, sizeof(device_id)) == -1)
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continue;
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/* Find a Marvell system controller */
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if (vendor_id == PCI_VENDOR_MARVELL &&
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device_id == PCI_PRODUCT_MARVELL_MV64360)
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return 1;
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}
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return 0;
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}
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}
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return 0;
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}
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/* ARGSUSED */
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void
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gt_attach(device_t parent, device_t self, void *aux)
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{
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struct gt_softc *sc = device_private(self);
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#if NGTPCI > 0
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uint32_t busrange[2];
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int node;
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extern struct genppc_pci_chipset
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genppc_gtpci0_chipset, genppc_gtpci1_chipset;
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#endif
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bus_space_init(&pegasosii_gt_bs_tag, "gt",
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ex_storage, sizeof(ex_storage));
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sc->sc_dev = self;
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sc->sc_addr = 0x00000000;
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sc->sc_iot = &pegasosii_gt_bs_tag;
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sc->sc_dmat = &pegasosii_bus_dma_tag;
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if (bus_space_map(sc->sc_iot, sc->sc_addr, GT_SIZE, 0, &sc->sc_ioh) !=
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0) {
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aprint_error(": registers map failed\n");
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return;
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}
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init_ofppc_interrupt();
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#if NGTPCI > 0
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/* bus space map the I/O and Memory ranges of PCI unit 1(PCI bus) */
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node = of_find_firstchild_byname(OF_finddevice("/"), "pci");
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if (node != -1) {
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gtpci1_io_bs_tag.pbs_flags =
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_BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_IO_TYPE;
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gtpci1_io_bs_tag.pbs_base = 0x00000000;
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if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node,
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>pci1_io_bs_tag, "gtpci 1 io-space") != 0)
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panic("Can't init gtpci 1 io tag");
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gtpci1_mem_bs_tag.pbs_flags =
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_BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE;
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gtpci1_mem_bs_tag.pbs_base = 0x00000000;
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if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node,
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>pci1_mem_bs_tag, "gtpci 1 mem-space") != 0)
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panic("Can't init gtpci 1 mem tag");
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/* PCI bus number */
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if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) !=
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sizeof(busrange)) {
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aprint_error(": PCI bus range failed\n");
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return;
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}
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/* Override some functions */
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genppc_gtpci1_chipset.pc_attach_hook = gtpci_md_attach_hook;
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genppc_gtpci1_chipset.pc_intr_map = genofw_pci_intr_map;
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genppc_gtpci1_chipset.pc_node = node;
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genppc_gtpci1_chipset.pc_bus = busrange[0];
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genppc_gtpci1_chipset.pc_iot = >pci1_io_bs_tag;
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genppc_gtpci1_chipset.pc_memt = >pci1_mem_bs_tag;
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#if NISA > 0
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genppc_isa_io_space_tag = gtpci1_io_bs_tag;
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genppc_isa_mem_space_tag = gtpci1_mem_bs_tag;
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map_isa_ioregs();
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ofppc_init_comcons(of_find_firstchild_byname(node, "isa"));
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#endif
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}
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/* bus space map the I/O and Memory ranges of PCI unit 0(AGP bus) */
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if (node != -1)
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node = of_getnode_byname(OF_peer(node), "pci");
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if (node != -1 && node != 0) {
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gtpci0_io_bs_tag.pbs_flags =
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_BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_IO_TYPE;
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gtpci0_io_bs_tag.pbs_base = 0x00000000;
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if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node,
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>pci0_io_bs_tag, "gtpci 0 io-space") != 0)
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panic("Can't init gtpci 0 io tag");
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gtpci0_mem_bs_tag.pbs_flags =
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_BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE;
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gtpci0_mem_bs_tag.pbs_base = 0x00000000;
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if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node,
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>pci0_mem_bs_tag, "gtpci 0 mem-space") != 0)
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panic("Can't init gtpci 0 mem tag");
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/* PCI bus number */
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if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) !=
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sizeof(busrange)) {
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aprint_error(": AGP bus range failed\n");
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return;
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}
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genppc_gtpci0_chipset.pc_node = node;
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genppc_gtpci0_chipset.pc_bus = busrange[0];
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genppc_gtpci0_chipset.pc_iot = >pci0_io_bs_tag;
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genppc_gtpci0_chipset.pc_memt = >pci0_mem_bs_tag;
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/* Enable AGP configuration space access. */
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bus_space_write_4(sc->sc_iot, sc->sc_ioh,
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GT_GPP_Value_Set, PEGASOS2_AGP_CONF_ENABLE);
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}
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#endif
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gt_attach_common(sc);
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}
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#if NGTPCI > 0
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static void
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gtpci_md_attach_hook(device_t parent, device_t self,
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struct pcibus_attach_args *pba)
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{
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extern struct genppc_pci_chipset genppc_gtpci1_chipset;
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if (device_is_a(parent, "gtpci") &&
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pba->pba_pc == &genppc_gtpci1_chipset) {
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/* Setup interrupts for PCI bus */
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struct genppc_pci_chipset_businfo *pbi;
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pbi = malloc(sizeof(struct genppc_pci_chipset_businfo),
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M_DEVBUF, M_NOWAIT);
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KASSERT(pbi != NULL);
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pbi->pbi_properties = prop_dictionary_create();
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KASSERT(pbi->pbi_properties != NULL);
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SIMPLEQ_INIT(&genppc_gtpci1_chipset.pc_pbi);
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SIMPLEQ_INSERT_TAIL(&genppc_gtpci1_chipset.pc_pbi, pbi, next);
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genofw_setup_pciintr_map(&genppc_gtpci1_chipset, pbi,
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genppc_gtpci1_chipset.pc_node);
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}
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gtpci_attach_hook(parent, self, pba);
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}
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/* ARGSUSED */
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void
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gtpci_md_conf_interrupt(void * v, int bus, int dev, int pin, int swiz,
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int *iline)
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{
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/* do nothing */
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}
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int
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gtpci_md_conf_hook(void *v, int bus, int dev, int func, pcireg_t id)
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{
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struct gtpci_softc *sc = v;
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if (gtpci_conf_hook(sc->sc_pc, bus, dev, func, id) == 0)
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return 0;
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return genofw_pci_conf_hook(sc->sc_pc, bus, dev, func, id);
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}
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#endif
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void *
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marvell_intr_establish(int irq, int ipl, int (*func)(void *), void *arg)
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{
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/* pass through */
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return intr_establish(irq, IST_LEVEL, ipl, func, arg);
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}
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