mhitch e48c624741 Loading the exception return PC in k0 before restoring the status register ... (which disables the interrupts) is *not* a good idea. k0 (and k1) is used by the kernel code such as the TLB miss handler, and the interrupt entry. If an interrupt occurs after loading k0 and before the SR gets interrupts disabled, k0 will be clobbered and when used to load the PC on exit from the exception handler, results in various hangs and crashes.		2000-02-23 17:04:06 +00:00
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conf	Allow arch-specific code to specify in4_cksum() like it can specify	2000-02-14 21:42:50 +00:00
include	mips is now vm_offset_t/vm_size_t clean	2000-02-22 12:28:25 +00:00
mips	Loading the exception return PC in k0 before restoring the status register	2000-02-23 17:04:06 +00:00
Makefile	…
Makefile.inc	…