471e528b58
struct timeval passed to todr_gettime(9) and todr_settime(9). We no longer have an ancient and volatile struct timeval `time' global since we have switched to MI timercounter(9) on all port. XXX1: some of these RTC drivers still assume 32bit time_t XXX2: some of these should be rewritten to use todr_[gs]ettime_ymdhms() XXX3: todr(9) man page doesn't mention todr_[gs]ettime_ymdhms()
474 lines
13 KiB
C
474 lines
13 KiB
C
/* $NetBSD: max6900.c,v 1.12 2009/12/12 14:44:10 tsutsui Exp $ */
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/*
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* Copyright (c) 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: max6900.c,v 1.12 2009/12/12 14:44:10 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/fcntl.h>
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#include <sys/uio.h>
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#include <sys/conf.h>
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#include <sys/event.h>
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#include <dev/clock_subr.h>
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#include <dev/i2c/i2cvar.h>
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#include <dev/i2c/max6900reg.h>
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struct maxrtc_softc {
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device_t sc_dev;
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i2c_tag_t sc_tag;
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int sc_address;
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int sc_open;
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struct todr_chip_handle sc_todr;
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};
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static int maxrtc_match(device_t, cfdata_t, void *);
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static void maxrtc_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(maxrtc, sizeof(struct maxrtc_softc),
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maxrtc_match, maxrtc_attach, NULL, NULL);
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extern struct cfdriver maxrtc_cd;
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dev_type_open(maxrtc_open);
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dev_type_close(maxrtc_close);
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dev_type_read(maxrtc_read);
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dev_type_write(maxrtc_write);
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const struct cdevsw maxrtc_cdevsw = {
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maxrtc_open, maxrtc_close, maxrtc_read, maxrtc_write, noioctl,
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nostop, notty, nopoll, nommap, nokqfilter, D_OTHER
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};
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static int maxrtc_clock_read(struct maxrtc_softc *, struct clock_ymdhms *);
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static int maxrtc_clock_write(struct maxrtc_softc *, struct clock_ymdhms *);
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static int maxrtc_gettime(struct todr_chip_handle *, struct timeval *);
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static int maxrtc_settime(struct todr_chip_handle *, struct timeval *);
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int
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maxrtc_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct i2c_attach_args *ia = aux;
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if ((ia->ia_addr & MAX6900_ADDRMASK) == MAX6900_ADDR)
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return (1);
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return (0);
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}
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void
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maxrtc_attach(device_t parent, device_t self, void *aux)
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{
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struct maxrtc_softc *sc = device_private(self);
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struct i2c_attach_args *ia = aux;
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sc->sc_tag = ia->ia_tag;
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sc->sc_address = ia->ia_addr;
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sc->sc_dev = self;
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aprint_naive(": Real-time Clock/NVRAM\n");
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aprint_normal(": MAX6900 Real-time Clock/NVRAM\n");
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sc->sc_open = 0;
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sc->sc_todr.cookie = sc;
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sc->sc_todr.todr_gettime = maxrtc_gettime;
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sc->sc_todr.todr_settime = maxrtc_settime;
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sc->sc_todr.todr_setwen = NULL;
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todr_attach(&sc->sc_todr);
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}
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/*ARGSUSED*/
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int
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maxrtc_open(dev_t dev, int flag, int fmt, struct lwp *l)
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{
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struct maxrtc_softc *sc;
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if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL)
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return (ENXIO);
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/* XXX: Locking */
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if (sc->sc_open)
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return (EBUSY);
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sc->sc_open = 1;
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return (0);
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}
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/*ARGSUSED*/
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int
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maxrtc_close(dev_t dev, int flag, int fmt, struct lwp *l)
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{
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struct maxrtc_softc *sc;
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if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL)
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return (ENXIO);
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sc->sc_open = 0;
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return (0);
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}
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/*ARGSUSED*/
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int
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maxrtc_read(dev_t dev, struct uio *uio, int flags)
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{
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struct maxrtc_softc *sc;
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u_int8_t ch, cmdbuf[1];
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int a, error;
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if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL)
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return (ENXIO);
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if (uio->uio_offset >= MAX6900_RAM_BYTES)
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return (EINVAL);
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if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
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return (error);
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while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) {
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a = (int)uio->uio_offset;
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cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_READ;
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if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP,
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sc->sc_address, cmdbuf, 1,
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&ch, 1, 0)) != 0) {
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iic_release_bus(sc->sc_tag, 0);
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aprint_error_dev(sc->sc_dev,
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"maxrtc_read: read failed at 0x%x\n", a);
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return (error);
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}
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if ((error = uiomove(&ch, 1, uio)) != 0) {
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iic_release_bus(sc->sc_tag, 0);
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return (error);
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}
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}
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iic_release_bus(sc->sc_tag, 0);
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return (0);
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}
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/*ARGSUSED*/
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int
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maxrtc_write(dev_t dev, struct uio *uio, int flags)
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{
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struct maxrtc_softc *sc;
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u_int8_t cmdbuf[2];
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int a, error, sverror;
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if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL)
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return (ENXIO);
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if (uio->uio_offset >= MAX6900_RAM_BYTES)
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return (EINVAL);
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if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
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return (error);
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/* Start by clearing the control register's write-protect bit. */
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cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE;
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cmdbuf[1] = 0;
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if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
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cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
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iic_release_bus(sc->sc_tag, 0);
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aprint_error_dev(sc->sc_dev,
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"maxrtc_write: failed to clear WP bit\n");
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return (error);
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}
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while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) {
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a = (int)uio->uio_offset;
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cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_WRITE;
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if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0)
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break;
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if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
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cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
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aprint_error_dev(sc->sc_dev,
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"maxrtc_write: write failed at 0x%x\n", a);
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break;
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}
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}
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/* Set the write-protect bit again. */
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cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE;
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cmdbuf[1] = MAX6900_CONTROL_WP;
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sverror = error;
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if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP,
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sc->sc_address, cmdbuf, 1,
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&cmdbuf[1], 1, 0)) != 0) {
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if (sverror != 0)
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error = sverror;
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aprint_error_dev(sc->sc_dev,
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"maxrtc_write: failed to set WP bit\n");
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}
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iic_release_bus(sc->sc_tag, 0);
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return (error);
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}
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static int
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maxrtc_gettime(struct todr_chip_handle *ch, struct timeval *tv)
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{
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struct maxrtc_softc *sc = ch->cookie;
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struct clock_ymdhms dt;
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if (maxrtc_clock_read(sc, &dt) == 0)
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return (-1);
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tv->tv_sec = clock_ymdhms_to_secs(&dt);
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tv->tv_usec = 0;
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return (0);
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}
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static int
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maxrtc_settime(struct todr_chip_handle *ch, struct timeval *tv)
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{
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struct maxrtc_softc *sc = ch->cookie;
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struct clock_ymdhms dt;
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clock_secs_to_ymdhms(tv->tv_sec, &dt);
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if (maxrtc_clock_write(sc, &dt) == 0)
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return (-1);
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return (0);
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}
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/*
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* While the MAX6900 has a nice Clock Burst Read/Write command,
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* we can't use it, since some I2C controllers do not support
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* anything other than single-byte transfers.
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*/
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static int max6900_rtc_offset[] = {
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MAX6900_REG_SECOND,
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MAX6900_REG_MINUTE,
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MAX6900_REG_HOUR,
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MAX6900_REG_DATE,
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MAX6900_REG_MONTH,
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MAX6900_REG_DAY,
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MAX6900_REG_YEAR,
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MAX6900_REG_CENTURY, /* control, if burst */
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};
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static int
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maxrtc_clock_read(struct maxrtc_softc *sc, struct clock_ymdhms *dt)
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{
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u_int8_t bcd[MAX6900_BURST_LEN], cmdbuf[1];
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int i;
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if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) {
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aprint_error_dev(sc->sc_dev,
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"maxrtc_clock_read: failed to acquire I2C bus\n");
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return (0);
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}
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/* Read each timekeeping register in order. */
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for (i = 0; i < MAX6900_BURST_LEN; i++) {
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cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_READ;
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if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP,
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sc->sc_address, cmdbuf, 1,
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&bcd[i], 1, I2C_F_POLL)) {
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iic_release_bus(sc->sc_tag, I2C_F_POLL);
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aprint_error_dev(sc->sc_dev,
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"maxrtc_clock_read: failed to read rtc "
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"at 0x%x\n",
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max6900_rtc_offset[i]);
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return (0);
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}
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}
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/* Done with I2C */
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iic_release_bus(sc->sc_tag, I2C_F_POLL);
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/*
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* Convert the MAX6900's register values into something useable
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*/
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dt->dt_sec = FROMBCD(bcd[MAX6900_BURST_SECOND] & MAX6900_SECOND_MASK);
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dt->dt_min = FROMBCD(bcd[MAX6900_BURST_MINUTE] & MAX6900_MINUTE_MASK);
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if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS) {
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dt->dt_hour = FROMBCD(bcd[MAX6900_BURST_HOUR] &
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MAX6900_HOUR_12MASK);
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if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS_PM)
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dt->dt_hour += 12;
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} else {
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dt->dt_hour = FROMBCD(bcd[MAX6900_BURST_HOUR] &
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MAX6900_HOUR_24MASK);
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}
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dt->dt_day = FROMBCD(bcd[MAX6900_BURST_DATE] & MAX6900_DATE_MASK);
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dt->dt_mon = FROMBCD(bcd[MAX6900_BURST_MONTH] & MAX6900_MONTH_MASK);
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dt->dt_year = FROMBCD(bcd[MAX6900_BURST_YEAR]);
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/* century in the burst control slot */
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dt->dt_year += (int)FROMBCD(bcd[MAX6900_BURST_CONTROL]) * 100;
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return (1);
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}
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static int
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maxrtc_clock_write(struct maxrtc_softc *sc, struct clock_ymdhms *dt)
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{
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uint8_t bcd[MAX6900_BURST_LEN], cmdbuf[2];
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uint8_t init_seconds, final_seconds;
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int i;
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/*
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* Convert our time representation into something the MAX6900
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* can understand.
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*/
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bcd[MAX6900_BURST_SECOND] = TOBCD(dt->dt_sec);
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bcd[MAX6900_BURST_MINUTE] = TOBCD(dt->dt_min);
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bcd[MAX6900_BURST_HOUR] = TOBCD(dt->dt_hour) & MAX6900_HOUR_24MASK;
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bcd[MAX6900_BURST_DATE] = TOBCD(dt->dt_day);
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bcd[MAX6900_BURST_WDAY] = TOBCD(dt->dt_wday);
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bcd[MAX6900_BURST_MONTH] = TOBCD(dt->dt_mon);
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bcd[MAX6900_BURST_YEAR] = TOBCD(dt->dt_year % 100);
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/* century in control slot */
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bcd[MAX6900_BURST_CONTROL] = TOBCD(dt->dt_year / 100);
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if (iic_acquire_bus(sc->sc_tag, I2C_F_POLL)) {
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aprint_error_dev(sc->sc_dev,
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"maxrtc_clock_write: failed to acquire I2C bus\n");
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return (0);
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}
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/* Start by clearing the control register's write-protect bit. */
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cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE;
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cmdbuf[1] = 0;
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if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
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cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) {
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iic_release_bus(sc->sc_tag, I2C_F_POLL);
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aprint_error_dev(sc->sc_dev,
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"maxrtc_clock_write: failed to clear WP bit\n");
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return (0);
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}
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/*
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* The MAX6900 RTC manual recommends ensuring "atomicity" of
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* a non-burst write by:
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*
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* - writing SECONDS
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* - reading back SECONDS, remembering it as "initial seconds"
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* - write the remaing RTC registers
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* - read back SECONDS as "final seconds"
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* - if "initial seconds" == 59, ensure "final seconds" == 59
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* - else, ensure "final seconds" is no more than one second
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* beyond "initial seconds".
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*/
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again:
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cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_WRITE;
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if (iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
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cmdbuf, 1, &bcd[MAX6900_BURST_SECOND], 1, I2C_F_POLL)) {
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iic_release_bus(sc->sc_tag, I2C_F_POLL);
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aprint_error_dev(sc->sc_dev,
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"maxrtc_clock_write: failed to write SECONDS\n");
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return (0);
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}
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cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ;
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if (iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address,
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cmdbuf, 1, &init_seconds, 1, I2C_F_POLL)) {
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iic_release_bus(sc->sc_tag, I2C_F_POLL);
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aprint_error_dev(sc->sc_dev,
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"maxrtc_clock_write: failed to read "
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"INITIAL SECONDS\n");
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return (0);
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}
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for (i = 1; i < MAX6900_BURST_LEN; i++) {
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cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_WRITE;
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if (iic_exec(sc->sc_tag,
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i != MAX6900_BURST_LEN - 1 ? I2C_OP_WRITE :
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I2C_OP_WRITE_WITH_STOP, sc->sc_address,
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cmdbuf, 1, &bcd[i], 1, I2C_F_POLL)) {
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iic_release_bus(sc->sc_tag, I2C_F_POLL);
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aprint_error_dev(sc->sc_dev,
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"maxrtc_clock_write: failed to write rtc "
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" at 0x%x\n",
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max6900_rtc_offset[i]);
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return (0);
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}
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}
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cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ;
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if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address,
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cmdbuf, 1, &final_seconds, 1, I2C_F_POLL)) {
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iic_release_bus(sc->sc_tag, I2C_F_POLL);
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aprint_error_dev(sc->sc_dev,
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"maxrtc_clock_write: failed to read "
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"FINAL SECONDS\n");
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return (0);
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}
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if ((init_seconds == 59 && final_seconds != 59) ||
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|
(init_seconds != 59 && final_seconds != init_seconds + 1)) {
|
|
#if 1
|
|
printf("%s: maxrtc_clock_write: init %d, final %d, try again\n",
|
|
device_xname(sc->sc_dev), init_seconds, final_seconds);
|
|
#endif
|
|
goto again;
|
|
}
|
|
|
|
/* Finish by setting the control register's write-protect bit. */
|
|
cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE;
|
|
cmdbuf[1] = MAX6900_CONTROL_WP;
|
|
|
|
if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address,
|
|
cmdbuf, 1, &cmdbuf[1], 1, I2C_F_POLL)) {
|
|
iic_release_bus(sc->sc_tag, I2C_F_POLL);
|
|
aprint_error_dev(sc->sc_dev,
|
|
"maxrtc_clock_write: failed to set WP bit\n");
|
|
return (0);
|
|
}
|
|
|
|
iic_release_bus(sc->sc_tag, I2C_F_POLL);
|
|
|
|
return (1);
|
|
}
|