2413e475f1
Interface card's Z8536 CIO for Timecounter support. Builds, should work, but not testable yet because of pmap breakage.
248 lines
11 KiB
C
248 lines
11 KiB
C
/* $NetBSD: z8536reg.h,v 1.3 2012/01/31 22:13:19 hauke Exp $ */
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/*-
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* Copyright (c) 2008 Hauke Fath
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Zilog Z8536 CIO (Counter/Timer and Parallel I/O Unit)
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* Register Definitions
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*
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* The CIO has four registers: One control register, and three data
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* registers for ports A/B/C. To set up the CIO through the control
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* register, first write the number of the internal register to it,
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* then access or set the selected register contents. Once selected,
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* an internal register can be polled continuously by reading out the
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* control port.
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*
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* Internal registers are read-writable, except where noted.
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*/
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#define Z8536_IOSIZE 0x04
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#define Z8536_MICR 0x00 /* Master Interrupt Control Register */
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#define MICR_RESET 0x01 /* Chip Reset */
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#define MICR_RJA 0x02 /* Only z8036 (ZBUS version) */
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#define MICR_CTVIS 0x04 /* CT vector includes status */
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#define MICR_PBVIS 0x08 /* Port B vector includes status */
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#define MICR_PAVIS 0x10 /* Port A vector includes status */
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#define MICR_NV 0x20 /* No Vector (NV) */
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#define MICR_DLC 0x40 /* Disable Lower Chain (DLC) */
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#define MICR_MIE 0x80 /* Master Interrupt Enable (MIE) */
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#define Z8536_MCCR 0x01 /* Master Configuration Register */
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#define MCCR_CTINDPT 0x00 /* Counter/Timers Independent */
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#define MCCR_CT1GT2 0x01 /* CT 1 /OUTPUT gates CT 2 */
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#define MCCR_CT1TR2 0x02 /* CT 1 /OUTPUT triggers CT 2 */
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#define MCCR_CT1CT2 0x03 /* CT 1 /OUTPUT is CT 2's COUNT */
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#define MCCR_PAE 0x04 /* Port A Enable */
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#define MCCR_PLC 0x08 /* Port Link Control (A/B) */
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#define MCCR_PC_CT3E 0x10 /* Counter/Timer 3 + Port C Enable */
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#define MCCR_CT2E 0x20 /* Counter/Timer 2 Enable */
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#define MCCR_CT1E 0x40 /* Counter/Timer 1 Enable */
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#define MCCR_PBE 0x80 /* Port B Enable */
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/* Interrupt Vector Registers */
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#define Z8536_IVRA 0x02 /* Port A Interrupt Vector */
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#define Z8536_IVRB 0x03 /* Port B Interrupt Vector */
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#define Z8536_IVRCT 0x04 /* Counter/Timer Interrupt Vector */
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/* Port C setup */
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#define Z8536_DPPRC 0x05 /* Port C Data Path Polarity */
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#define Z8536_DDRC 0x06 /* Port C Data Direction */
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#define Z8536_SIOCRC 0x07 /* Port C Special I/O Control */
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#define Z8536_PCSRA 0x08 /* Port A Command and Status */
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#define Z8536_PCSRB 0x09 /* Port B Command and Status */
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/* Z8536_PCSRA + Z8536_PCSRB command and status bits */
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#define PCSR_IOE 0x01 /* Interrupt on error */
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#define PCSR_PMF 0x02 /* Pattern match flag (RO) */
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#define PCSR_IRF 0x04 /* Input register full (RO) */
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#define PCSR_ORE 0x08 /* Output register empty (RO) */
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#define PCSR_ERR 0x10 /* Interrupt error */
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#define PCSR_IP 0x20 /* Interrupt pending */
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#define PCSR_IE 0x40 /* Interrupt enable */
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#define PCSR_IUS 0x80 /* Interrupt under service */
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/* PCSR{A,B} interrupt bits: IUS/IE/IP */
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#define PCSR_NULL 0x00 /* Null Code */
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#define PCSR_CLR_IP_IUS 0x20 /* Clear IP and IUS */
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#define PCSR_SET_IUS 0x40 /* Set Interrupt Under Service */
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#define PCSR_CLR_IUS 0x60 /* Clear Interrupt Under Service */
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#define PCSR_SET_IP 0x80 /* Set Interrupt Pending */
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#define PCSR_CLR_IP 0xA0 /* Clear Interrupt Pending */
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#define PCSR_SET_IE 0xC0 /* Set Interrupt Enable */
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#define PCSR_CLR_IE 0xE0 /* Clear Interrupt Enable */
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/* Counter/Timer 1..3 Command and Status Registers */
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#define Z8536_CTCSR1 0x0A /* CT 1 Command and Status */
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#define Z8536_CTCSR2 0x0B /* CT 2 Command and Status */
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#define Z8536_CTCSR3 0x0C /* CT 3 Command and Status */
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/* CTCSR setup bits */
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#define CTCS_CIP 0x01 /* Count in Progress (RO) */
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#define CTCS_TCB 0x02 /* Trigger Command Bit (WO) */
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#define CTCS_GCB 0x04 /* Gate Command Bit */
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#define CTCS_RCC 0x08 /* Read Counter Control */
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#define CTCS_ERR 0x10 /* Interrupt Error (RO) */
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#define CTCS_IP 0x20 /* Interrupt Pending */
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#define CTCS_IE 0x40 /* Interrupt Enable */
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#define CTCS_IUS 0x80 /* Interrupt Under Service */
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/* CTCSR interrupt bits: IUS/IE/IP */
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#define CTCS_NULL 0x00 /* Null Code */
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#define CTCS_CLR_IP_IUS 0x20 /* Clear IP and IUS */
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#define CTCS_SET_IUS 0x40 /* Set Interrupt Under Service */
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#define CTCS_CLR_IUS 0x60 /* Clear Interrupt Under Service */
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#define CTCS_SET_IP 0x80 /* Set Interrupt Pending */
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#define CTCS_CLR_IP 0xA0 /* Clear Interrupt Pending */
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#define CTCS_SET_IE 0xC0 /* Set Interrupt Enable */
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#define CTCS_CLR_IE 0xE0 /* Clear Interrupt Enable */
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/* Avoid changing intr bits unintendedly */
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#define CTCSR_MASK(FLAGS) ((FLAGS) & 0x3f)
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/* The port data registers are directly accessible at their own IO address */
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#define Z8536_PDRA 0x0D /* Port A Data Register */
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#define Z8536_PDRB 0x0E /* Port B Data Register */
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#define Z8536_PDRC 0x0F /* Port C Data Register */
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/* Bytewise access to current count registers (read-only) */
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#define Z8536_CTCCR1_MSB 0x10 /* CT 1 Current Count MSB */
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#define Z8536_CTCCR1_LSB 0x11 /* CT 1 Current Count LSB */
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#define Z8536_CTCCR2_MSB 0x12 /* CT 2 Current Count MSB */
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#define Z8536_CTCCR2_LSB 0x13 /* CT 2 Current Count LSB */
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#define Z8536_CTCCR3_MSB 0x14 /* CT 3 Current Count MSB */
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#define Z8536_CTCCR3_LSB 0x15 /* CT 3 Current Count LSB */
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/* Bytewise access to time constant registers */
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#define Z8536_CTTCR1_MSB 0x16 /* CT 1 Time Constant MSB */
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#define Z8536_CTTCR1_LSB 0x17 /* CT 1 Time Constant LSB */
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#define Z8536_CTTCR2_MSB 0x18 /* CT 2 Time Constant MSB */
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#define Z8536_CTTCR2_LSB 0x19 /* CT 2 Time Constant LSB */
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#define Z8536_CTTCR3_MSB 0x1A /* CT 3 Time Constant MSB */
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#define Z8536_CTTCR3_LSB 0x1B /* CT 3 Time Constant LSB */
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/* Counter/Timer Mode specification */
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#define Z8536_CTMSR1 0x1C /* CT 1 Mode Specification */
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#define Z8536_CTMSR2 0x1D /* CT 2 Mode Specification */
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#define Z8536_CTMSR3 0x1E /* CT 3 Mode Specification */
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#define CTMS_DCS_PULSE 0x00 /* Pulse Output */
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#define CTMS_DCS_ONESHOT 0x01 /* One-Shot Output */
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#define CTMS_DCS_SQUARE 0x02 /* Square Wave Output */
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#define CTMS_REB 0x04 /* Retrigger Enable */
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#define CTMS_EGE 0x08 /* External Gate Enable */
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#define CTMS_ETE 0x10 /* External Trigger Enable */
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#define CTMS_ECE 0x20 /* External Count Enable */
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#define CTMS_EOE 0x40 /* External Output Enable */
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#define CTMS_CSC 0x80 /* Continuous / Single Cycle */
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#define Z8536_CVR 0x1F /* Current Interrupt Vector (RO) */
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/* Port A specification registers */
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#define Z8536_PMSRA 0x20 /* Port A Mode Specification */
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#define Z8536_PHSRA 0x21 /* Port A Handshake Specification */
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#define Z8536_DPPRA 0x22 /* Port A Data Path Polarity */
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#define Z8536_DDRA 0x23 /* Port A Data Direction */
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#define Z8536_SIOCRA 0x24 /* Port A Special I/O Control */
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#define Z8536_PPRA 0x25 /* Port A Pattern Polarity */
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#define Z8536_PTRA 0x26 /* Port A Pattern Transition */
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#define Z8536_PMRA 0x27 /* Port A Pattern Mask */
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/* Port B specification registers */
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#define Z8536_PMSRB 0x28 /* Port B Mode Specification */
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#define Z8536_PHSRB 0x29 /* Port B Handshake Specification */
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#define Z8536_DPPRB 0x2A /* Port B Data Path Polarity */
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#define Z8536_DDRB 0x2B /* Port B Data Direction */
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#define Z8536_SIOCRB 0x2C /* Port B Special I/O Control */
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#define Z8536_PPRB 0x2D /* Port B Pattern Polarity */
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#define Z8536_PTRB 0x2E /* Port B Pattern Transition */
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#define Z8536_PMRB 0x2F /* Port B Pattern Mask */
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/* Bit definitions, common to ports A and B */
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/* Z8536_PMSRA + Z8536_PMSRB port mode specification bits */
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#define PMSR_LPM 0x01 /* Bit mode: latched */
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#define PMSR_DTE 0x01 /* Hsk mode: deskew timer enable */
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/*
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* PMS1 PMS0 Pattern mode specification
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* 0 0 disable pattern match
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* 0 1 "and" mode, transition-triggered interrupt
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* 1 0 "or" mode, transition-triggered interrupt
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* 1 1 "or-priority encoded vector" mode, level-
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* triggered interrupt (only transparent LPM mode)
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*/
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#define PMSR_PMS0 0x02
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#define PMSR_PMS1 0x04
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#define PMSR_PMS_OFF 0x00 /* Disable pattern match */
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#define PMSR_PMS_AND 0x02 /* "and" mode, transition-triggered */
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#define PMSR_PMS_OR 0x04 /* "or" mode, transition-triggered */
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/*
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* "or-priority encoded vector" mode, level-triggered interrupt
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* (only in transparent LPM mode)
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*/
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#define PMSR_PMS_OR_PEV 0x06
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#define PMSR_IMO 0x08 /* Interrupt on match only */
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#define PMSR_SB 0x10 /* Single buffered mode */
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#define PMSR_ITB 0x20 /* Interrupt on two bytes */
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/*
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* PTS1 PTS0 Port type selects
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* 0 0 bit port
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* 0 1 input port
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* 1 0 output port
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* 1 1 bidirectional port
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*/
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#define PMSR_PTS0 0x40
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#define PMSR_PTS1 0x80
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#define PMSR_PTS_BIT 0x00
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#define PMSR_PTS_IN 0x40
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#define PMSR_PTS_OUT 0x80
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#define PMSR_PTS_BIDI 0xC0
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/*
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* Z8536_PHSRA + Z8536_PHSRB port handshake specification bits
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* Bits 0-2 set deskew timer for output ports
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*
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* RWS2 RWS1 RWS0 Status signals on port C
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* 0 0 0 REQUEST/-WAIT disabled
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* 0 0 1 output -WAIT
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* 0 1 1 input -WAIT
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* 1 0 0 special REQUEST
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* 1 0 1 output REQUEST
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* 1 1 1 input REQUEST
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*/
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#define PHSR_RWS0 0x08
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#define PHSR_RWS1 0x10
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#define PHSR_RWS2 0x20
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/*
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* HTS1 HTS0 Handshake type specification
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* 0 0 interlocked handshake
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* 0 1 strobed handshake
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* 1 0 pulsed handshake
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* 1 1 three-wire-handshake
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*/
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#define PHSR_HTS0 0x40
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#define PHSR_HTS1 0x80
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#define PHSR_HTS_INT 0x00
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#define PHSR_HTS_STR 0x40
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#define PHSR_HTS_PUL 0x80
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#define PHSR_HTS_TWI 0xC0
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