212 lines
7.3 KiB
C
212 lines
7.3 KiB
C
/* $NetBSD: pte.h,v 1.5 1999/06/05 21:58:18 eeh Exp $ */
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/*
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* Copyright (c) 1996-1999 Eduardo Horvath
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Address translation works as follows:
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*
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**
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* For sun4u:
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*
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* Take your pick; it's all S/W anyway. We'll start by emulating a sun4.
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* Oh, here's the sun4u TTE for reference:
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*
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* struct sun4u_tte {
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* u_int64 tag_g:1, (global flag)
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* tag_ctxt:15, (context for mapping)
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* tag_unassigned:6,
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* tag_va:42; (virtual address bits<64:22>)
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* u_int64 data_v:1, (valid bit)
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* data_size:2, (page size [8K*8**<SIZE>])
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* data_nfo:1, (no-fault only)
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* data_ie:1, (invert endianness [inefficient])
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* data_soft2:2, (reserved for S/W)
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* data_pa:36, (physical address)
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* data_soft:6, (reserved for S/W)
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* data_lock:1, (lock into TLB)
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* data_cacheable:2, (cacheability control)
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* data_e:1, (explicit accesses only)
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* data_priv:1, (privileged page)
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* data_w:1, (writeable)
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* data_g:1; (same as tag_g)
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* };
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*/
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/* virtual address to virtual page number */
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#define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31)
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/* virtual address to offset within page */
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#define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF)
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/* When we go to 64-bit VAs we need to handle the hole */
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#define VA_VPG(va) VA_SUN4U_VPG(va)
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#define VA_OFF(va) VA_SUN4U_OFF(va)
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#define PG_SHIFT4U 13
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#define MMU_PAGE_ALIGN 8192
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/* If you know where a tte is in the tsb, how do you find its va? */
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#define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000))
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#ifndef _LOCORE
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/*
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* This is the spitfire TTE.
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*
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* We could use bitmasks and shifts to construct this if
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* we had a 64-bit compiler w/64-bit longs. Otherwise it's
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* a real pain to do this in C.
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*/
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struct sun4u_tag_fields {
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u_int64_t tag_g:1, /* global flag */
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tag_ctxt:15, /* context for mapping */
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tag_unassigned:6,
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tag_va:42; /* virtual address bits<64:22> */
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};
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union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; };
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struct sun4u_data_fields {
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u_int64_t data_v:1, /* valid bit */
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data_size:2, /* page size [8K*8**<SIZE>] */
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data_nfo:1, /* no-fault only */
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data_ie:1, /* invert endianness [inefficient] */
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data_soft2:2, /* reserved for S/W */
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data_pa:36, /* physical address */
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data_accessed:1,/* S/W accessed bit */
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data_modified:1,/* S/W modified bit */
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data_realw:1, /* S/W real writable bit (to manage modified) */
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data_tsblock:1, /* S/W TSB locked entry */
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data_exec:1, /* S/W Executable */
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data_onlyexec:1,/* S/W Executable only */
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data_lock:1, /* lock into TLB */
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data_cacheable:2, /* cacheability control */
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data_e:1, /* explicit accesses only */
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data_priv:1, /* privileged page */
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data_w:1, /* writeable */
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data_g:1; /* same as tag_g */
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};
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union sun4u_data { struct sun4u_data_fields f; int64_t data; };
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struct sun4u_tte {
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union sun4u_tag tag;
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union sun4u_data data;
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};
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typedef struct sun4u_tte pte_t;
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/* Assembly routine to flush a mapping */
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extern void tlb_flush_pte __P((vaddr_t addr, int ctx));
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extern void tlb_flush_ctx __P((int ctx));
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#endif /* _LOCORE */
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/* TSB tag masks */
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#define CTX_MASK ((1<<13)-1)
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#define TSB_TAG_CTX_SHIFT 48
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#define TSB_TAG_VA_SHIFT 22
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#define TSB_TAG_G 0x8000000000000000LL
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#define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK)
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#define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT))
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#define TSB_TAG(g,ctx,va) ((((u_int64_t)((g)!=0))<<63)|(((u_int64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((u_int64_t)va)>>TSB_TAG_VA_SHIFT))
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/* TLB data masks */
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#define TLB_V 0x8000000000000000LL
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#define TLB_8K 0x0000000000000000LL
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#define TLB_64K 0x2000000000000000LL
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#define TLB_512K 0x4000000000000000LL
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#define TLB_4M 0x6000000000000000LL
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#define TLB_SZ_MASK 0x6000000000000000LL
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#define TLB_NFO 0x1000000000000000LL
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#define TLB_IE 0x0800000000000000LL
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#define TLB_SOFT2_MASK 0x07fe000000000000LL
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#define TLB_DIAG_MASK 0x0001fe0000000000LL
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#define TLB_PA_MASK 0x000001ffffffe000LL
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#define TLB_SOFT_MASK 0x0000000000001f80LL
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/* S/W bits */
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/* Access & TSB locked bits are swapped so I can set access w/one insn */
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/* #define TLB_ACCESS 0x0000000000001000LL */
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#define TLB_ACCESS 0x0000000000000200LL
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#define TLB_MODIFY 0x0000000000000800LL
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#define TLB_REAL_W 0x0000000000000400LL
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/* #define TLB_TSB_LOCK 0x0000000000000200LL */
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#define TLB_TSB_LOCK 0x0000000000001000LL
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#define TLB_EXEC 0x0000000000000100LL
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#define TLB_EXEC_ONLY 0x0000000000000080LL
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/* H/W bits */
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#define TLB_L 0x0000000000000040LL
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#define TLB_CACHE_MASK 0x0000000000000030LL
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#define TLB_CP 0x0000000000000020LL
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#define TLB_CV 0x0000000000000010LL
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#define TLB_E 0x0000000000000008LL
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#define TLB_P 0x0000000000000004LL
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#define TLB_W 0x0000000000000002LL
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#define TLB_G 0x0000000000000001LL
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/*
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* The following bits are used by locore so they should
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* be duplicates of the above w/o the "long long"
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*/
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/* S/W bits */
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/* #define TTE_ACCESS 0x0000000000001000 */
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#define TTE_ACCESS 0x0000000000000200
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#define TTE_MODIFY 0x0000000000000800
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#define TTE_REAL_W 0x0000000000000400
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/* #define TTE_TSB_LOCK 0x0000000000000200 */
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#define TTE_TSB_LOCK 0x0000000000001000
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#define TTE_EXEC 0x0000000000000100
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#define TTE_EXEC_ONLY 0x0000000000000080
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/* H/W bits */
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#define TTE_L 0x0000000000000040
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#define TTE_CACHE_MASK 0x0000000000000030
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#define TTE_CP 0x0000000000000020
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#define TTE_CV 0x0000000000000010
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#define TTE_E 0x0000000000000008
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#define TTE_P 0x0000000000000004
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#define TTE_W 0x0000000000000002
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#define TTE_G 0x0000000000000001
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#define TTE_DATA_BITS "\177\20" \
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"b\77V\0" "f\75\2SIZE\0" "b\77V\0" "f\75\2SIZE\0" \
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"=\0008K\0" "=\00164K\0" "=\002512K\0" "=\0034M\0" \
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"b\74NFO\0" "b\73IE\0" "f\62\10SOFT2\0" \
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"f\51\10DIAG\0" "f\15\33PA<40:13>\0" "f\7\5SOFT\0" \
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"b\6L\0" "b\5CP\0" "b\4CV\0" \
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"b\3E\0" "b\2P\0" "b\1W\0" "b\0G\0"
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#define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
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(((valid)?TLB_V:0LL)|(sz)|(((u_int64_t)(pa))&TLB_PA_MASK)|\
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((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\
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((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)|((ie)?TLB_IE:0LL))
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#define MMU_CACHE_VIRT 0x3
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#define MMU_CACHE_PHYS 0x2
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#define MMU_CACHE_NONE 0x0
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/* This needs to be updated for sun4u IOMMUs */
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/*
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* IOMMU PTE bits.
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*/
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#define IOPTE_PPN_MASK 0x07ffff00
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#define IOPTE_PPN_SHIFT 8
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#define IOPTE_RSVD 0x000000f1
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#define IOPTE_WRITE 0x00000004
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#define IOPTE_VALID 0x00000002
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