167 lines
4.9 KiB
C
167 lines
4.9 KiB
C
/* $NetBSD: intcreg.h,v 1.2 1999/09/16 12:48:35 msaitoh Exp $ */
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/*-
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH3_INTCREG_H__
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#define _SH3_INTCREG_H__
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#ifndef BYTE_ORDER
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#error Define BYTE_ORDER!
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#endif
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/*
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* Interrupt Controller
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*/
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struct sh3_intc {
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/* Interrupt control register (0xFFFFFEE0) */
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union {
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unsigned short WORD; /* Word Access */
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struct { /* Bit Access */
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#if BYTE_ORDER == BIG_ENDIAN
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/* Bit 15..0 */
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unsigned char NMIL:1;
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unsigned char :6;
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unsigned char NMIE:1;
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unsigned char :8;
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#else /* BYTE_ORDER == LITTLE_ENDIAN */
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/* Bit 0..15 */
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unsigned char :8;
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unsigned char NMIE:1;
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unsigned char :6;
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unsigned char NMIL:1;
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#endif
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} BIT;
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} ICR;
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/* Interrupt priority setting register A (FFFFFEE2) */
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union {
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unsigned short WORD; /* Word Access */
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struct { /* Bit Access */
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#if BYTE_ORDER == BIG_ENDIAN
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/* Bit 15..0 */
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unsigned short TMU0 :4;
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unsigned short TMU1 :4;
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unsigned short TMU2 :4;
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unsigned short RTC :4;
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#else /* BYTE_ORDER == LITTLE_ENDIAN */
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/* Bit 0..15 */
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unsigned short RTC :4;
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unsigned short TMU2 :4;
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unsigned short TMU1 :4;
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unsigned short TMU0 :4;
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#endif
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} BIT;
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} IPRA;
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/* Interrupt priority setting register B (FFFFFEE4) */
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union {
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unsigned short WORD; /* Word Access */
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struct { /* Bit Access */
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#if BYTE_ORDER == BIG_ENDIAN
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/* Bit 15..0 */
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unsigned short WDT :4;
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unsigned short REF :4;
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unsigned short SCI :4;
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unsigned short :4;
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#else /* BYTE_ORDER == LITTLE_ENDIAN */
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/* Bit 0..15 */
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unsigned short :4;
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unsigned short SCI :4;
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unsigned short REF :4;
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unsigned short WDT :4;
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#endif
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} BIT;
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} IPRB;
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};
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/* address definitions for interrupt controller (INTC)*/
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#if !defined(SH4)
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/* SH3 definition */
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#define SHREG_ICR0 (*(volatile unsigned short *)0xfffffee0)
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#define SHREG_IPRA (*(volatile unsigned short *)0xfffffee2)
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#define SHREG_IPRB (*(volatile unsigned short *)0xfffffee4)
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#if defined(SH7709) || defined(SH7709A)
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#define SHREG_ICR1 (*(volatile unsigned short *)0xa4000010)
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#define SHREG_ICR2 (*(volatile unsigned short *)0xa4000012)
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#define SHREG_PINTER (*(volatile unsigned short *)0xa4000014)
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#define SHREG_IPRC (*(volatile unsigned short *)0xa4000016)
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#define SHREG_IPRD (*(volatile unsigned short *)0xa4000018)
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#define SHREG_IPRE (*(volatile unsigned short *)0xa400001a)
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#define SHREG_IRR0 (*(volatile unsigned char *)0xa4000004)
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#define SHREG_IRR1 (*(volatile unsigned char *)0xa4000006)
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#define SHREG_IRR2 (*(volatile unsigned char *)0xa4000008)
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#define IPRC_IRQ3_MASK 0xf000
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#define IPRC_IRQ2_MASK 0x0f00
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#define IPRC_IRQ1_MASK 0x00f0
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#define IPRC_IRQ0_MASK 0x000f
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#define IPRD_PINT07_MASK 0xf000
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#define IPRD_PINT8F_MASK 0x0f00
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#define IPRD_IRQ5_MASK 0x00f0
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#define IPRD_IRQ4_MASK 0x000f
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#define IPRE_DMAC_MASK 0xf000
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#define IPRE_IRDA_MASK 0x0f00
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#define IPRE_SCIF_MASK 0x00f0
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#define IPRE_ADC_MASK 0x000f
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#endif
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#else
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/* SH4 definitions */
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#define SHREG_ICR (*(volatile unsigned short *)0xffd00000)
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#define SHREG_IPRA (*(volatile unsigned short *)0xffd00004)
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#define SHREG_IPRB (*(volatile unsigned short *)0xffd00008)
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#define SHREG_IPRC (*(volatile unsigned short *)0xffd0000c)
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#define IPRC_GPIO_MASK 0xf000
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#define IPRC_DMAC_MASK 0x0f00
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#define IPRC_SCIF_MASK 0x00f0
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#define IPRC_HUDI_MASK 0x000f
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#endif
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#define IPRA_TMU0_MASK 0xf000
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#define IPRA_TMU1_MASK 0x0f00
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#define IPRA_TMU2_MASK 0x00f0
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#define IPRA_RTC_MASK 0x000f
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#define IPRB_WDT_MASK 0xf000
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#define IPRB_REF_MASK 0x0f00
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#define IPRB_SCI_MASK 0x00f0
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#endif /* !_SH3_INTCREG_H__ */
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