e8823cc3f3
* Macroize hardware and software descriptor access (much easier to read). * Simplify and optimize the transmit loop a bit, and use IFF_OACTIVE as appropriate. * Fix a potential race condition in the transmit loop. This change has made the driver significantly more stable (almost completely eliminated the "device timeout" errors that have plagued this driver). * Implement transmit interrupt pacing. * Add missing bus_dmamap_sync() calls (on transmit and receive descriptors and fraglists). (Draining the write buffer when accessing these structures may have also contributed to the increased stability of this driver on the Alpha.)
180 lines
6.2 KiB
C
180 lines
6.2 KiB
C
/* $NetBSD: smc83c170var.h,v 1.3 1999/02/12 05:55:27 thorpej Exp $ */
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/*-
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* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_SMC83C170VAR_H_
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#define _DEV_IC_SMC83C170VAR_H_
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/*
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* Misc. definitions for the Standard Microsystems Corp. 83C170
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* Ethernet PCI Integrated Controller (EPIC/100) driver.
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*/
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/*
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* Transmit descriptor list size.
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*/
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#define EPIC_NTXDESC 128
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#define EPIC_NTXDESC_MASK (EPIC_NTXDESC - 1)
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#define EPIC_NEXTTX(x) ((x + 1) & EPIC_NTXDESC_MASK)
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/*
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* Receive descriptor list size.
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*/
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#define EPIC_NRXDESC 64
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#define EPIC_NRXDESC_MASK (EPIC_NRXDESC - 1)
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#define EPIC_NEXTRX(x) ((x + 1) & EPIC_NRXDESC_MASK)
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/*
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* Control structures are DMA'd to the EPIC chip. We allocate them in
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* a single clump that maps to a single DMA segment to make several things
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* easier.
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*/
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struct epic_control_data {
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/*
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* The transmit descriptors.
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*/
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struct epic_txdesc ecd_txdescs[EPIC_NTXDESC];
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/*
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* The receive descriptors.
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*/
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struct epic_rxdesc ecd_rxdescs[EPIC_NRXDESC];
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/*
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* The transmit fraglists.
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*/
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struct epic_fraglist ecd_txfrags[EPIC_NTXDESC];
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};
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#define EPIC_CDOFF(x) offsetof(struct epic_control_data, x)
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#define EPIC_CDTXOFF(x) EPIC_CDOFF(ecd_txdescs[(x)])
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#define EPIC_CDRXOFF(x) EPIC_CDOFF(ecd_rxdescs[(x)])
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#define EPIC_CDFLOFF(x) EPIC_CDOFF(ecd_txfrags[(x)])
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/*
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* Software state for transmit and receive desciptors.
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*/
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struct epic_descsoft {
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struct mbuf *ds_mbuf; /* head of mbuf chain */
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bus_dmamap_t ds_dmamap; /* our DMA map */
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};
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/*
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* Software state per device.
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*/
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struct epic_softc {
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struct device sc_dev; /* generic device information */
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bus_space_tag_t sc_st; /* bus space tag */
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bus_space_handle_t sc_sh; /* bus space handle */
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bus_dma_tag_t sc_dmat; /* bus DMA tag */
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struct ethercom sc_ethercom; /* ethernet common data */
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void *sc_sdhook; /* shutdown hook */
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struct mii_data sc_mii; /* MII/media information */
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bus_dmamap_t sc_cddmamap; /* control data DMA map */
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#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
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/*
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* Software state for transmit and receive descriptors.
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*/
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struct epic_descsoft sc_txsoft[EPIC_NTXDESC];
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struct epic_descsoft sc_rxsoft[EPIC_NRXDESC];
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/*
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* Control data structures.
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*/
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struct epic_control_data *sc_control_data;
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int sc_txpending; /* number of TX requests pending */
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int sc_txdirty; /* first dirty TX descriptor */
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int sc_txlast; /* last used TX descriptor */
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int sc_rxptr; /* next ready RX descriptor */
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};
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#define EPIC_CDTXADDR(sc, x) ((sc)->sc_cddma + EPIC_CDTXOFF((x)))
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#define EPIC_CDRXADDR(sc, x) ((sc)->sc_cddma + EPIC_CDRXOFF((x)))
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#define EPIC_CDFLADDR(sc, x) ((sc)->sc_cddma + EPIC_CDFLOFF((x)))
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#define EPIC_CDTX(sc, x) (&(sc)->sc_control_data->ecd_txdescs[(x)])
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#define EPIC_CDRX(sc, x) (&(sc)->sc_control_data->ecd_rxdescs[(x)])
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#define EPIC_CDFL(sc, x) (&(sc)->sc_control_data->ecd_txfrags[(x)])
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#define EPIC_DSTX(sc, x) (&(sc)->sc_txsoft[(x)])
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#define EPIC_DSRX(sc, x) (&(sc)->sc_rxsoft[(x)])
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#define EPIC_CDTXSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
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EPIC_CDTXOFF((x)), sizeof(struct epic_txdesc), (ops))
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#define EPIC_CDRXSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
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EPIC_CDRXOFF((x)), sizeof(struct epic_rxdesc), (ops))
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#define EPIC_CDFLSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
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EPIC_CDFLOFF((x)), sizeof(struct epic_fraglist), (ops))
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#define EPIC_INIT_RXDESC(sc, x) \
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do { \
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struct epic_descsoft *__ds = EPIC_DSRX((sc), (x)); \
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struct epic_rxdesc *__rxd = EPIC_CDRX((sc), (x)); \
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struct mbuf *__m = __ds->ds_mbuf; \
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\
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/* \
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* Note we scoot the packet forward 2 bytes in the buffer \
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* so that the payload after the Ethernet header is aligned \
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* to a 4 byte boundary. \
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*/ \
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__m->m_data = __m->m_ext.ext_buf + 2; \
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__rxd->er_bufaddr = __ds->ds_dmamap->dm_segs[0].ds_addr + 2; \
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__rxd->er_buflength = __m->m_ext.ext_size - 2; \
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__rxd->er_control = 0; \
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__rxd->er_rxstatus = ER_RXSTAT_OWNER; \
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__rxd->er_nextdesc = EPIC_CDRXADDR((sc), EPIC_NEXTRX((x))); \
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EPIC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
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} while (0)
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#ifdef _KERNEL
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void epic_attach __P((struct epic_softc *));
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int epic_intr __P((void *));
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#endif /* _KERNEL */
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#endif /* _DEV_IC_SMC83C170VAR_H_ */
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