354 lines
9.0 KiB
C
354 lines
9.0 KiB
C
/* $NetBSD: mlx_eisa.c,v 1.22 2009/05/12 14:21:32 cegger Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Andrew Doran.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* EISA front-end for mlx(4) driver.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mlx_eisa.c,v 1.22 2009/05/12 14:21:32 cegger Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <dev/eisa/eisavar.h>
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#include <dev/eisa/eisadevs.h>
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#include <dev/ic/mlxreg.h>
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#include <dev/ic/mlxio.h>
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#include <dev/ic/mlxvar.h>
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#define MLX_EISA_SLOT_OFFSET 0x0c80
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#define MLX_EISA_IOSIZE (0x0ce0 - MLX_EISA_SLOT_OFFSET)
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#define MLX_EISA_CFG01 (0x0cc0 - MLX_EISA_SLOT_OFFSET)
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#define MLX_EISA_CFG02 (0x0cc1 - MLX_EISA_SLOT_OFFSET)
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#define MLX_EISA_CFG03 (0x0cc3 - MLX_EISA_SLOT_OFFSET)
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#define MLX_EISA_CFG04 (0x0c8d - MLX_EISA_SLOT_OFFSET)
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#define MLX_EISA_CFG05 (0x0c90 - MLX_EISA_SLOT_OFFSET)
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#define MLX_EISA_CFG06 (0x0c91 - MLX_EISA_SLOT_OFFSET)
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#define MLX_EISA_CFG07 (0x0c92 - MLX_EISA_SLOT_OFFSET)
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#define MLX_EISA_CFG08 (0x0c93 - MLX_EISA_SLOT_OFFSET)
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#define MLX_EISA_CFG09 (0x0c94 - MLX_EISA_SLOT_OFFSET)
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#define MLX_EISA_CFG10 (0x0c95 - MLX_EISA_SLOT_OFFSET)
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static void mlx_eisa_attach(device_t, device_t, void *);
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static int mlx_eisa_match(device_t, cfdata_t, void *);
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static int mlx_v1_submit(struct mlx_softc *, struct mlx_ccb *);
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static int mlx_v1_findcomplete(struct mlx_softc *, u_int *, u_int *);
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static void mlx_v1_intaction(struct mlx_softc *, int);
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static int mlx_v1_fw_handshake(struct mlx_softc *, int *, int *, int *);
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#ifdef MLX_RESET
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static int mlx_v1_reset(struct mlx_softc *);
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#endif
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CFATTACH_DECL(mlx_eisa, sizeof(struct mlx_softc),
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mlx_eisa_match, mlx_eisa_attach, NULL, NULL);
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static struct mlx_eisa_prod {
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const char *mp_idstr;
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int mp_nchan;
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} const mlx_eisa_prod[] = {
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{ "MLX0070", 1 },
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{ "MLX0071", 3 },
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{ "MLX0072", 3 },
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{ "MLX0073", 2 },
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{ "MLX0074", 1 },
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{ "MLX0075", 3 },
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{ "MLX0076", 2 },
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{ "MLX0077", 1 },
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};
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static int
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mlx_eisa_match(device_t parent, cfdata_t match,
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void *aux)
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{
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struct eisa_attach_args *ea;
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int i;
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ea = aux;
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for (i = 0; i < sizeof(mlx_eisa_prod) / sizeof(mlx_eisa_prod[0]); i++)
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if (strcmp(ea->ea_idstring, mlx_eisa_prod[i].mp_idstr) == 0)
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return (1);
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return (0);
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}
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static void
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mlx_eisa_attach(device_t parent, device_t self, void *aux)
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{
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struct eisa_attach_args *ea;
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bus_space_handle_t ioh;
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eisa_chipset_tag_t ec;
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eisa_intr_handle_t ih;
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struct mlx_softc *mlx;
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bus_space_tag_t iot;
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const char *intrstr;
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int irq, i, icfg;
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ea = aux;
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mlx = device_private(self);
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iot = ea->ea_iot;
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ec = ea->ea_ec;
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if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
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MLX_EISA_SLOT_OFFSET, MLX_EISA_IOSIZE, 0, &ioh)) {
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printf("can't map i/o space\n");
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return;
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}
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mlx->mlx_iot = iot;
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mlx->mlx_ioh = ioh;
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mlx->mlx_dmat = ea->ea_dmat;
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/*
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* Map and establish the interrupt.
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*/
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icfg = bus_space_read_1(iot, ioh, MLX_EISA_CFG03);
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switch (icfg & 0xf0) {
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case 0xa0:
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irq = 11;
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break;
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case 0xc0:
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irq = 12;
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break;
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case 0xe0:
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irq = 14;
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break;
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case 0x80:
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irq = 15;
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break;
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default:
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printf("controller on invalid IRQ\n");
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return;
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}
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if (eisa_intr_map(ec, irq, &ih)) {
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printf("can't map interrupt (%d)\n", irq);
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return;
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}
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intrstr = eisa_intr_string(ec, ih);
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mlx->mlx_ih = eisa_intr_establish(ec, ih,
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((icfg & 0x08) != 0 ? IST_LEVEL : IST_EDGE),
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IPL_BIO, mlx_intr, mlx);
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if (mlx->mlx_ih == NULL) {
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printf("can't establish interrupt");
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if (intrstr != NULL)
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printf(" at %s", intrstr);
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printf("\n");
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return;
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}
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for (i = 0; i < sizeof(mlx_eisa_prod) / sizeof(mlx_eisa_prod[0]); i++)
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if (strcmp(ea->ea_idstring, mlx_eisa_prod[i].mp_idstr) == 0) {
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mlx->mlx_ci.ci_nchan = mlx_eisa_prod[i].mp_nchan;
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break;
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}
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mlx->mlx_ci.ci_iftype = 1;
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mlx->mlx_submit = mlx_v1_submit;
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mlx->mlx_findcomplete = mlx_v1_findcomplete;
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mlx->mlx_intaction = mlx_v1_intaction;
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mlx->mlx_fw_handshake = mlx_v1_fw_handshake;
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#ifdef MLX_RESET
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mlx->mlx_reset = mlx_v1_reset;
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#endif
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printf(": Mylex RAID\n");
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mlx_init(mlx, intrstr);
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}
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/*
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* ================= V1 interface linkage =================
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*/
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/*
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* Try to give (mc) to the controller. Returns 1 if successful, 0 on
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* failure (the controller is not ready to take a command).
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*
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* Must be called at splbio or in a fashion that prevents reentry.
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*/
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static int
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mlx_v1_submit(struct mlx_softc *mlx, struct mlx_ccb *mc)
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{
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/* Ready for our command? */
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if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_FULL) == 0) {
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/* Copy mailbox data to window. */
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bus_space_write_region_1(mlx->mlx_iot, mlx->mlx_ioh,
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MLX_V1REG_MAILBOX, mc->mc_mbox, 13);
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bus_space_barrier(mlx->mlx_iot, mlx->mlx_ioh,
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MLX_V1REG_MAILBOX, 13,
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BUS_SPACE_BARRIER_WRITE);
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/* Post command. */
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mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_FULL);
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return (1);
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}
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return (0);
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}
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/*
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* See if a command has been completed, if so acknowledge its completion and
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* recover the slot number and status code.
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*
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* Must be called at splbio or in a fashion that prevents reentry.
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*/
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static int
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mlx_v1_findcomplete(struct mlx_softc *mlx, u_int *slot, u_int *status)
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{
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/* Status available? */
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if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_SAVAIL) != 0) {
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*slot = mlx_inb(mlx, MLX_V1REG_MAILBOX + 0x0d);
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*status = mlx_inw(mlx, MLX_V1REG_MAILBOX + 0x0e);
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/* Acknowledge completion. */
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mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_SAVAIL);
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mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK);
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return (1);
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}
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return (0);
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}
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/*
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* Enable/disable interrupts as requested. (No acknowledge required)
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*
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* Must be called at splbio or in a fashion that prevents reentry.
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*/
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static void
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mlx_v1_intaction(struct mlx_softc *mlx, int action)
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{
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mlx_outb(mlx, MLX_V1REG_IE, action ? 1 : 0);
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}
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/*
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* Poll for firmware error codes during controller initialisation.
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*
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* Returns 0 if initialisation is complete, 1 if still in progress but no
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* error has been fetched, 2 if an error has been retrieved.
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*/
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static int
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mlx_v1_fw_handshake(struct mlx_softc *mlx, int *error, int *param1, int *param2)
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{
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u_int8_t fwerror;
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/*
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* First time around, enable the IDB interrupt and clear any
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* hardware completion status.
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*/
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if ((mlx->mlx_flags & MLXF_FW_INITTED) == 0) {
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mlx_outb(mlx, MLX_V1REG_ODB_EN, 1);
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DELAY(1000);
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mlx_outb(mlx, MLX_V1REG_ODB, 1);
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DELAY(1000);
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mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK);
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DELAY(1000);
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mlx->mlx_flags |= MLXF_FW_INITTED;
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}
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/* Init in progress? */
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if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_INIT_BUSY) == 0)
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return (0);
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/* Test error value. */
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fwerror = mlx_inb(mlx, MLX_V1REG_ODB);
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if ((fwerror & MLX_V1_FWERROR_PEND) == 0)
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return (1);
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/* XXX Fetch status. */
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*error = fwerror & 0xf0;
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*param1 = -1;
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*param2 = -1;
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/* Acknowledge. */
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mlx_outb(mlx, MLX_V1REG_ODB, fwerror);
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return (2);
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}
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#ifdef MLX_RESET
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/*
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* Reset the controller. Return non-zero on failure.
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*/
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static int
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mlx_v1_reset(struct mlx_softc *mlx)
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{
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int i;
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mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_SACK);
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delay(1000000);
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/* Wait up to 2 minutes for the bit to clear. */
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for (i = 120; i != 0; i--) {
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delay(1000000);
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if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_SACK) == 0)
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break;
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}
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if (i == 0)
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return (-1);
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mlx_outb(mlx, MLX_V1REG_ODB, MLX_V1_ODB_RESET);
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mlx_outb(mlx, MLX_V1REG_IDB, MLX_V1_IDB_RESET);
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/* Wait up to 5 seconds for the bit to clear... */
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for (i = 5; i != 0; i--) {
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delay(1000000);
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if ((mlx_inb(mlx, MLX_V1REG_IDB) & MLX_V1_IDB_RESET) == 0)
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break;
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}
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if (i == 0)
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return (-1);
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/* Wait up to 3 seconds for the other bit to clear... */
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for (i = 5; i != 0; i--) {
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delay(1000000);
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if ((mlx_inb(mlx, MLX_V1REG_ODB) & MLX_V1_ODB_RESET) == 0)
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break;
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}
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if (i == 0)
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return (-1);
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return (0);
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}
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#endif /* MLX_RESET */
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