850 lines
24 KiB
C
850 lines
24 KiB
C
/* $NetBSD: if_gmc.c,v 1.5 2012/07/22 14:32:50 matt Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas <matt@3am-software.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/callout.h>
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#include <sys/device.h>
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#include <sys/ioctl.h>
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#include <sys/kernel.h>
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#include <sys/kmem.h>
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#include <sys/mbuf.h>
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#include <sys/bus.h>
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#include <machine/intr.h>
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#include <arm/gemini/gemini_reg.h>
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#include <arm/gemini/gemini_gmacreg.h>
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#include <arm/gemini/gemini_gmacvar.h>
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#include <net/if.h>
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#include <net/if_ether.h>
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#include <net/if_dl.h>
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__KERNEL_RCSID(0, "$NetBSD: if_gmc.c,v 1.5 2012/07/22 14:32:50 matt Exp $");
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#define MAX_TXSEG 32
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struct gmc_softc {
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device_t sc_dev;
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struct gmac_softc *sc_psc;
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struct gmc_softc *sc_sibling;
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bus_dma_tag_t sc_dmat;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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bus_space_handle_t sc_dma_ioh;
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bus_space_handle_t sc_gmac_ioh;
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struct ethercom sc_ec;
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struct mii_data sc_mii;
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void *sc_ih;
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bool sc_port1;
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uint8_t sc_phy;
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gmac_hwqueue_t *sc_rxq;
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gmac_hwqueue_t *sc_txq[6];
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callout_t sc_mii_ch;
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uint32_t sc_gmac_status;
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uint32_t sc_gmac_sta_add[3];
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uint32_t sc_gmac_mcast_filter[2];
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uint32_t sc_gmac_rx_filter;
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uint32_t sc_gmac_config[2];
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uint32_t sc_dmavr;
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uint32_t sc_int_mask[5];
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uint32_t sc_int_enabled[5];
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};
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#define sc_if sc_ec.ec_if
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static bool
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gmc_txqueue(struct gmc_softc *sc, gmac_hwqueue_t *hwq, struct mbuf *m)
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{
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bus_dmamap_t map;
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uint32_t desc0, desc1, desc3;
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struct mbuf *last_m, *m0;
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size_t count, i;
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int error;
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gmac_desc_t *d;
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KASSERT(hwq != NULL);
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map = gmac_mapcache_get(hwq->hwq_hqm->hqm_mc);
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if (map == NULL)
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return false;
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for (last_m = NULL, m0 = m, count = 0;
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m0 != NULL;
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last_m = m0, m0 = m0->m_next) {
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vaddr_t addr = (uintptr_t)m0->m_data;
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if (m0->m_len == 0)
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continue;
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if (addr & 1) {
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if (last_m != NULL && M_TRAILINGSPACE(last_m) > 0) {
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last_m->m_data[last_m->m_len++] = *m->m_data++;
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m->m_len--;
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} else if (M_TRAILINGSPACE(m0) > 0) {
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memmove(m0->m_data + 1, m0->m_data, m0->m_len);
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m0->m_data++;
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} else if (M_LEADINGSPACE(m0) > 0) {
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memmove(m0->m_data - 1, m0->m_data, m0->m_len);
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m0->m_data--;
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} else {
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panic("gmc_txqueue: odd addr %p", m0->m_data);
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}
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}
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count += ((addr & PGOFSET) + m->m_len + PGOFSET) >> PGSHIFT;
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}
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gmac_hwqueue_sync(hwq);
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if (hwq->hwq_free <= count) {
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gmac_mapcache_put(hwq->hwq_hqm->hqm_mc, map);
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return false;
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}
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error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
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BUS_DMA_WRITE|BUS_DMA_NOWAIT);
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if (error) {
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aprint_error_dev(sc->sc_dev, "ifstart: load failed: %d\n",
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error);
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gmac_mapcache_put(hwq->hwq_hqm->hqm_mc, map);
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m_freem(m);
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sc->sc_if.if_oerrors++;
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return true;
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}
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KASSERT(map->dm_nsegs > 0);
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/*
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* Sync the mbuf contents to memory/cache.
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*/
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bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
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BUS_DMASYNC_PREWRITE);
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/*
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* Now we need to load the descriptors...
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*/
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desc0 = map->dm_nsegs << 16;
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desc1 = m->m_pkthdr.len;
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desc3 = DESC3_SOF;
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i = 0;
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d = NULL;
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do {
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#if 0
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if (i > 0)
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aprint_debug_dev(sc->sc_dev,
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"gmac_txqueue: %zu@%p=%#x/%#x/%#x/%#x\n",
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i-1, d, d->d_desc0, d->d_desc1,
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d->d_bufaddr, d->d_desc3);
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#endif
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d = gmac_hwqueue_desc(hwq, i);
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KASSERT(map->dm_segs[i].ds_len > 0);
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KASSERT((map->dm_segs[i].ds_addr & 1) == 0);
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d->d_desc0 = htole32(map->dm_segs[i].ds_len | desc0);
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d->d_desc1 = htole32(desc1);
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d->d_bufaddr = htole32(map->dm_segs[i].ds_addr);
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d->d_desc3 = htole32(desc3);
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desc3 = 0;
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} while (++i < map->dm_nsegs);
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d->d_desc3 |= htole32(DESC3_EOF|DESC3_EOFIE);
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#if 0
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aprint_debug_dev(sc->sc_dev,
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"gmac_txqueue: %zu@%p=%#x/%#x/%#x/%#x\n",
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i-1, d, d->d_desc0, d->d_desc1, d->d_bufaddr, d->d_desc3);
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#endif
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M_SETCTX(m, map);
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IF_ENQUEUE(&hwq->hwq_ifq, m);
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/*
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* Last descriptor has been marked. Give them to the h/w.
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* This will sync for us.
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*/
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gmac_hwqueue_produce(hwq, map->dm_nsegs);
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#if 0
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aprint_debug_dev(sc->sc_dev,
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"gmac_txqueue: *%zu@%p=%#x/%#x/%#x/%#x\n",
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i-1, d, d->d_desc0, d->d_desc1, d->d_bufaddr, d->d_desc3);
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#endif
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return true;
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}
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static void
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gmc_filter_change(struct gmc_softc *sc)
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{
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struct ether_multi *enm;
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struct ether_multistep step;
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uint32_t mhash[2];
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uint32_t new0, new1, new2;
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const char * const eaddr = CLLADDR(sc->sc_if.if_sadl);
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new0 = eaddr[0] | ((eaddr[1] | (eaddr[2] | (eaddr[3] << 8)) << 8) << 8);
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new1 = eaddr[4] | (eaddr[5] << 8);
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new2 = 0;
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if (sc->sc_gmac_sta_add[0] != new0
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|| sc->sc_gmac_sta_add[1] != new1
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|| sc->sc_gmac_sta_add[2] != new2) {
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bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_STA_ADD0,
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new0);
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bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_STA_ADD1,
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new1);
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bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_STA_ADD2,
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new2);
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sc->sc_gmac_sta_add[0] = new0;
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sc->sc_gmac_sta_add[1] = new1;
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sc->sc_gmac_sta_add[2] = new2;
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}
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mhash[0] = 0;
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mhash[1] = 0;
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ETHER_FIRST_MULTI(step, &sc->sc_ec, enm);
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while (enm != NULL) {
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size_t i;
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if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
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mhash[0] = mhash[1] = 0xffffffff;
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break;
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}
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i = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
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mhash[(i >> 5) & 1] |= 1 << (i & 31);
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ETHER_NEXT_MULTI(step, enm);
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}
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if (sc->sc_gmac_mcast_filter[0] != mhash[0]
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|| sc->sc_gmac_mcast_filter[1] != mhash[1]) {
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bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh,
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GMAC_MCAST_FILTER0, mhash[0]);
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bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh,
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GMAC_MCAST_FILTER1, mhash[1]);
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sc->sc_gmac_mcast_filter[0] = mhash[0];
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sc->sc_gmac_mcast_filter[1] = mhash[1];
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}
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new0 = sc->sc_gmac_rx_filter & ~RXFILTER_PROMISC;
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new0 |= RXFILTER_BROADCAST | RXFILTER_UNICAST | RXFILTER_MULTICAST;
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if (sc->sc_if.if_flags & IFF_PROMISC)
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new0 |= RXFILTER_PROMISC;
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if (new0 != sc->sc_gmac_rx_filter) {
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bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_RX_FILTER,
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new0);
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sc->sc_gmac_rx_filter = new0;
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}
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}
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static void
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gmc_mii_tick(void *arg)
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{
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struct gmc_softc * const sc = arg;
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struct gmac_softc * const psc = sc->sc_psc;
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int s = splnet();
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/*
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* If we had to increase the number of receive mbufs due to fifo
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* overflows, we need a way to decrease them. So every second we
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* recieve less than or equal to MIN_RXMAPS packets, we decrement
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* swfree_min until it returns to MIN_RXMAPS.
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*/
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if (psc->sc_rxpkts_per_sec <= MIN_RXMAPS
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&& psc->sc_swfree_min > MIN_RXMAPS) {
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psc->sc_swfree_min--;
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gmac_swfree_min_update(psc);
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}
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/*
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* If only one GMAC is running or this is port0, reset the count.
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*/
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if (psc->sc_running != 3 || !sc->sc_port1)
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psc->sc_rxpkts_per_sec = 0;
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mii_tick(&sc->sc_mii);
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if (sc->sc_if.if_flags & IFF_RUNNING)
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callout_schedule(&sc->sc_mii_ch, hz);
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splx(s);
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}
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static int
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gmc_mediachange(struct ifnet *ifp)
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{
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struct gmc_softc * const sc = ifp->if_softc;
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if ((ifp->if_flags & IFF_UP) == 0)
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return 0;
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return mii_mediachg(&sc->sc_mii);
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}
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static void
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gmc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
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{
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struct gmc_softc * const sc = ifp->if_softc;
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mii_pollstat(&sc->sc_mii);
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ifmr->ifm_status = sc->sc_mii.mii_media_status;
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ifmr->ifm_active = sc->sc_mii.mii_media_active;
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}
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static void
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gmc_mii_statchg(struct ifnet *ifp)
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{
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struct gmc_softc * const sc = ifp->if_softc;
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uint32_t gmac_status;
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gmac_status = sc->sc_gmac_status;
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gmac_status &= ~STATUS_PHYMODE_MASK;
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gmac_status |= STATUS_PHYMODE_RGMII_A;
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gmac_status &= ~STATUS_SPEED_MASK;
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if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_1000_T) {
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gmac_status |= STATUS_SPEED_1000M;
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} else if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) {
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gmac_status |= STATUS_SPEED_100M;
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} else {
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gmac_status |= STATUS_SPEED_10M;
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}
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if (sc->sc_mii.mii_media_active & IFM_FDX)
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gmac_status |= STATUS_DUPLEX_FULL;
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else
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gmac_status &= ~STATUS_DUPLEX_FULL;
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if (sc->sc_mii.mii_media_status & IFM_ACTIVE)
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gmac_status |= STATUS_LINK_ON;
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else
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gmac_status &= ~STATUS_LINK_ON;
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if (sc->sc_gmac_status != gmac_status) {
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aprint_debug_dev(sc->sc_dev,
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"status change old=%#x new=%#x active=%#x\n",
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sc->sc_gmac_status, gmac_status,
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sc->sc_mii.mii_media_active);
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sc->sc_gmac_status = gmac_status;
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bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_STATUS,
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sc->sc_gmac_status);
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}
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(*sc->sc_mii.mii_writereg)(sc->sc_dev, sc->sc_phy, 0x0018, 0x0041);
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}
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static int
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gmc_ifioctl(struct ifnet *ifp, u_long cmd, void *data)
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{
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struct gmc_softc * const sc = ifp->if_softc;
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struct ifreq * const ifr = data;
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int s;
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int error;
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s = splnet();
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switch (cmd) {
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case SIOCSIFMEDIA:
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case SIOCGIFMEDIA:
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error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
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break;
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default:
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error = ether_ioctl(ifp, cmd, data);
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if (error == ENETRESET) {
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if (ifp->if_flags & IFF_RUNNING) {
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/*
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* If the interface is running, we have to
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* update its multicast filter.
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*/
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gmc_filter_change(sc);
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}
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error = 0;
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}
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}
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splx(s);
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return error;
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}
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static void
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gmc_ifstart(struct ifnet *ifp)
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{
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struct gmc_softc * const sc = ifp->if_softc;
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#if 0
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if ((sc->sc_gmac_status & STATUS_LINK_ON) == 0)
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return;
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#endif
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if ((ifp->if_flags & IFF_RUNNING) == 0)
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return;
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for (;;) {
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struct mbuf *m;
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IF_DEQUEUE(&ifp->if_snd, m);
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if (m == NULL)
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break;
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if (!gmc_txqueue(sc, sc->sc_txq[0], m)) {
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IF_PREPEND(&ifp->if_snd, m);
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ifp->if_flags |= IFF_OACTIVE;
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break;
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}
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}
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}
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static void
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gmc_ifstop(struct ifnet *ifp, int disable)
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{
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struct gmc_softc * const sc = ifp->if_softc;
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struct gmac_softc * const psc = sc->sc_psc;
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psc->sc_running &= ~(sc->sc_port1 ? 2 : 1);
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psc->sc_int_enabled[0] &= ~sc->sc_int_enabled[0];
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psc->sc_int_enabled[1] &= ~sc->sc_int_enabled[1];
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psc->sc_int_enabled[2] &= ~sc->sc_int_enabled[2];
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psc->sc_int_enabled[3] &= ~sc->sc_int_enabled[3];
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psc->sc_int_enabled[4] &= ~sc->sc_int_enabled[4] | INT4_SW_FREEQ_EMPTY;
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if (psc->sc_running == 0) {
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psc->sc_int_enabled[4] &= ~INT4_SW_FREEQ_EMPTY;
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KASSERT(psc->sc_int_enabled[0] == 0);
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KASSERT(psc->sc_int_enabled[1] == 0);
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KASSERT(psc->sc_int_enabled[2] == 0);
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KASSERT(psc->sc_int_enabled[3] == 0);
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KASSERT(psc->sc_int_enabled[4] == 0);
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} else if (((psc->sc_int_select[4] & INT4_SW_FREEQ_EMPTY) != 0)
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== sc->sc_port1) {
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psc->sc_int_select[4] &= ~INT4_SW_FREEQ_EMPTY;
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK,
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psc->sc_int_select[4]);
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}
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gmac_intr_update(psc);
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if (disable) {
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#if 0
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if (psc->sc_running == 0) {
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gmac_mapcache_destroy(&psc->sc_txmaps);
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gmac_mapcache_destroy(&psc->sc_rxmaps);
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}
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#endif
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}
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}
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static int
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gmc_ifinit(struct ifnet *ifp)
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{
|
|
struct gmc_softc * const sc = ifp->if_softc;
|
|
struct gmac_softc * const psc = sc->sc_psc;
|
|
uint32_t new, mask;
|
|
|
|
gmac_mapcache_fill(psc->sc_rxmaps, MIN_RXMAPS);
|
|
gmac_mapcache_fill(psc->sc_txmaps, MIN_TXMAPS);
|
|
|
|
if (sc->sc_rxq == NULL) {
|
|
gmac_hwqmem_t *hqm;
|
|
hqm = gmac_hwqmem_create(psc->sc_rxmaps, 16, /*RXQ_NDESCS,*/ 1,
|
|
HQM_CONSUMER|HQM_RX);
|
|
sc->sc_rxq = gmac_hwqueue_create(hqm, sc->sc_iot,
|
|
sc->sc_ioh, GMAC_DEF_RXQn_RWPTR(sc->sc_port1),
|
|
GMAC_DEF_RXQn_BASE(sc->sc_port1), 0);
|
|
if (sc->sc_rxq == NULL) {
|
|
gmac_hwqmem_destroy(hqm);
|
|
goto failed;
|
|
}
|
|
sc->sc_rxq->hwq_ifp = ifp;
|
|
sc->sc_rxq->hwq_producer = psc->sc_swfreeq;
|
|
}
|
|
|
|
if (sc->sc_txq[0] == NULL) {
|
|
gmac_hwqueue_t *hwq, *last_hwq;
|
|
gmac_hwqmem_t *hqm;
|
|
size_t i;
|
|
|
|
hqm = gmac_hwqmem_create(psc->sc_txmaps, TXQ_NDESCS, 6,
|
|
HQM_PRODUCER|HQM_TX);
|
|
KASSERT(hqm != NULL);
|
|
for (i = 0; i < __arraycount(sc->sc_txq); i++) {
|
|
sc->sc_txq[i] = gmac_hwqueue_create(hqm, sc->sc_iot,
|
|
sc->sc_dma_ioh, GMAC_SW_TX_Qn_RWPTR(i),
|
|
GMAC_SW_TX_Q_BASE, i);
|
|
if (sc->sc_txq[i] == NULL) {
|
|
if (i == 0)
|
|
gmac_hwqmem_destroy(hqm);
|
|
goto failed;
|
|
}
|
|
sc->sc_txq[i]->hwq_ifp = ifp;
|
|
|
|
last_hwq = NULL;
|
|
SLIST_FOREACH(hwq, &psc->sc_hwfreeq->hwq_producers,
|
|
hwq_link) {
|
|
if (sc->sc_txq[i]->hwq_qoff < hwq->hwq_qoff)
|
|
break;
|
|
last_hwq = hwq;
|
|
}
|
|
if (last_hwq == NULL)
|
|
SLIST_INSERT_HEAD(
|
|
&psc->sc_hwfreeq->hwq_producers,
|
|
sc->sc_txq[i], hwq_link);
|
|
else
|
|
SLIST_INSERT_AFTER(last_hwq, sc->sc_txq[i],
|
|
hwq_link);
|
|
}
|
|
}
|
|
|
|
gmc_filter_change(sc);
|
|
|
|
mask = DMAVR_LOOPBACK|DMAVR_DROP_SMALL_ACK|DMAVR_EXTRABYTES_MASK
|
|
|DMAVR_RXBURSTSIZE_MASK|DMAVR_RXBUSWIDTH_MASK
|
|
|DMAVR_TXBURSTSIZE_MASK|DMAVR_TXBUSWIDTH_MASK;
|
|
new = DMAVR_RXDMA_ENABLE|DMAVR_TXDMA_ENABLE
|
|
|DMAVR_EXTRABYTES(2)
|
|
|DMAVR_RXBURSTSIZE(DMAVR_BURSTSIZE_32W)
|
|
|DMAVR_RXBUSWIDTH(DMAVR_BUSWIDTH_32BITS)
|
|
|DMAVR_TXBURSTSIZE(DMAVR_BURSTSIZE_32W)
|
|
|DMAVR_TXBUSWIDTH(DMAVR_BUSWIDTH_32BITS);
|
|
new |= sc->sc_dmavr & ~mask;
|
|
if (sc->sc_dmavr != new) {
|
|
sc->sc_dmavr = new;
|
|
bus_space_write_4(sc->sc_iot, sc->sc_dma_ioh, GMAC_DMAVR,
|
|
sc->sc_dmavr);
|
|
aprint_debug_dev(sc->sc_dev, "gmc_ifinit: dmavr=%#x/%#x\n",
|
|
sc->sc_dmavr,
|
|
bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, GMAC_DMAVR));
|
|
}
|
|
|
|
mask = CONFIG0_MAXLEN_MASK|CONFIG0_TX_DISABLE|CONFIG0_RX_DISABLE
|
|
|CONFIG0_LOOPBACK|/*CONFIG0_SIM_TEST|*/CONFIG0_INVERSE_RXC_RGMII
|
|
|CONFIG0_RGMII_INBAND_STATUS_ENABLE;
|
|
new = CONFIG0_MAXLEN(CONFIG0_MAXLEN_1536)|CONFIG0_R_LATCHED_MMII;
|
|
new |= (sc->sc_gmac_config[0] & ~mask);
|
|
if (sc->sc_gmac_config[0] != new) {
|
|
sc->sc_gmac_config[0] = new;
|
|
bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_CONFIG0,
|
|
sc->sc_gmac_config[0]);
|
|
aprint_debug_dev(sc->sc_dev, "gmc_ifinit: config0=%#x/%#x\n",
|
|
sc->sc_gmac_config[0],
|
|
bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_CONFIG0));
|
|
}
|
|
|
|
psc->sc_rxpkts_per_sec +=
|
|
gmac_rxproduce(psc->sc_swfreeq, psc->sc_swfree_min);
|
|
|
|
/*
|
|
* If we will be the only active interface, make sure the sw freeq
|
|
* interrupt gets routed to use.
|
|
*/
|
|
if (psc->sc_running == 0
|
|
&& (((psc->sc_int_select[4] & INT4_SW_FREEQ_EMPTY) != 0) != sc->sc_port1)) {
|
|
psc->sc_int_select[4] ^= INT4_SW_FREEQ_EMPTY;
|
|
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK,
|
|
psc->sc_int_select[4]);
|
|
}
|
|
sc->sc_int_enabled[0] = sc->sc_int_mask[0]
|
|
& (INT0_TXDERR|INT0_TXPERR|INT0_RXDERR|INT0_RXPERR|INT0_SWTXQ_EOF);
|
|
sc->sc_int_enabled[1] = sc->sc_int_mask[1] & INT1_DEF_RXQ_EOF;
|
|
sc->sc_int_enabled[4] = INT4_SW_FREEQ_EMPTY | (sc->sc_int_mask[4]
|
|
& (INT4_TX_FAIL|INT4_MIB_HEMIWRAP|INT4_RX_FIFO_OVRN
|
|
|INT4_RGMII_STSCHG));
|
|
|
|
psc->sc_int_enabled[0] |= sc->sc_int_enabled[0];
|
|
psc->sc_int_enabled[1] |= sc->sc_int_enabled[1];
|
|
psc->sc_int_enabled[4] |= sc->sc_int_enabled[4];
|
|
|
|
gmac_intr_update(psc);
|
|
|
|
if ((ifp->if_flags & IFF_RUNNING) == 0)
|
|
mii_tick(&sc->sc_mii);
|
|
|
|
ifp->if_flags |= IFF_RUNNING;
|
|
psc->sc_running |= (sc->sc_port1 ? 2 : 1);
|
|
|
|
callout_schedule(&sc->sc_mii_ch, hz);
|
|
|
|
return 0;
|
|
|
|
failed:
|
|
gmc_ifstop(ifp, true);
|
|
return ENOMEM;
|
|
}
|
|
|
|
static int
|
|
gmc_intr(void *arg)
|
|
{
|
|
struct gmc_softc * const sc = arg;
|
|
uint32_t int0_status, int1_status, int4_status;
|
|
uint32_t status;
|
|
bool do_ifstart = false;
|
|
int rv = 0;
|
|
|
|
aprint_debug_dev(sc->sc_dev, "gmac_intr: entry\n");
|
|
|
|
int0_status = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
|
|
GMAC_INT0_STATUS);
|
|
int1_status = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
|
|
GMAC_INT1_STATUS);
|
|
int4_status = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
|
|
GMAC_INT4_STATUS);
|
|
|
|
aprint_debug_dev(sc->sc_dev, "gmac_intr: sts=%#x/%#x/%#x/%#x/%#x\n",
|
|
int0_status, int1_status,
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS),
|
|
int4_status);
|
|
|
|
#if 0
|
|
aprint_debug_dev(sc->sc_dev, "gmac_intr: mask=%#x/%#x/%#x/%#x/%#x\n",
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_MASK),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_MASK),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_MASK),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_MASK),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK));
|
|
#endif
|
|
|
|
status = int0_status & sc->sc_int_mask[0];
|
|
if (status & (INT0_TXDERR|INT0_TXPERR)) {
|
|
aprint_error_dev(sc->sc_dev,
|
|
"transmit%s%s error: %#x %08x bufaddr %#x\n",
|
|
status & INT0_TXDERR ? " data" : "",
|
|
status & INT0_TXPERR ? " protocol" : "",
|
|
bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh,
|
|
GMAC_DMA_TX_CUR_DESC),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh,
|
|
GMAC_SW_TX_Q0_RWPTR),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh,
|
|
GMAC_DMA_TX_DESC2));
|
|
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS,
|
|
status & (INT0_TXDERR|INT0_TXPERR));
|
|
Debugger();
|
|
}
|
|
if (status & (INT0_RXDERR|INT0_RXPERR)) {
|
|
aprint_error_dev(sc->sc_dev,
|
|
"receive%s%s error: %#x %#x=%#x/%#x/%#x/%#x\n",
|
|
status & INT0_RXDERR ? " data" : "",
|
|
status & INT0_RXPERR ? " protocol" : "",
|
|
bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh,
|
|
GMAC_DMA_RX_CUR_DESC),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh,
|
|
GMAC_SWFREEQ_RWPTR),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh,
|
|
GMAC_DMA_RX_DESC0),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh,
|
|
GMAC_DMA_RX_DESC1),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh,
|
|
GMAC_DMA_RX_DESC2),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh,
|
|
GMAC_DMA_RX_DESC3));
|
|
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS,
|
|
status & (INT0_RXDERR|INT0_RXPERR));
|
|
Debugger();
|
|
}
|
|
if (status & INT0_SWTXQ_EOF) {
|
|
status &= INT0_SWTXQ_EOF;
|
|
for (int i = 0; status && i < __arraycount(sc->sc_txq); i++) {
|
|
if (status & INT0_SWTXQn_EOF(i)) {
|
|
gmac_hwqueue_sync(sc->sc_txq[i]);
|
|
bus_space_write_4(sc->sc_iot, sc->sc_ioh,
|
|
GMAC_INT0_STATUS,
|
|
sc->sc_int_mask[0] & (INT0_SWTXQn_EOF(i)|INT0_SWTXQn_FIN(i)));
|
|
status &= ~INT0_SWTXQn_EOF(i);
|
|
}
|
|
}
|
|
do_ifstart = true;
|
|
rv = 1;
|
|
}
|
|
|
|
if (int4_status & INT4_SW_FREEQ_EMPTY) {
|
|
struct gmac_softc * const psc = sc->sc_psc;
|
|
psc->sc_rxpkts_per_sec +=
|
|
gmac_rxproduce(psc->sc_swfreeq, psc->sc_swfree_min);
|
|
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS,
|
|
status & INT4_SW_FREEQ_EMPTY);
|
|
rv = 1;
|
|
}
|
|
|
|
status = int1_status & sc->sc_int_mask[1];
|
|
if (status & INT1_DEF_RXQ_EOF) {
|
|
struct gmac_softc * const psc = sc->sc_psc;
|
|
psc->sc_rxpkts_per_sec +=
|
|
gmac_hwqueue_consume(sc->sc_rxq, psc->sc_swfree_min);
|
|
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS,
|
|
status & INT1_DEF_RXQ_EOF);
|
|
rv = 1;
|
|
}
|
|
|
|
status = int4_status & sc->sc_int_enabled[4];
|
|
if (status & INT4_TX_FAIL) {
|
|
}
|
|
if (status & INT4_MIB_HEMIWRAP) {
|
|
}
|
|
if (status & INT4_RX_XON) {
|
|
}
|
|
if (status & INT4_RX_XOFF) {
|
|
}
|
|
if (status & INT4_TX_XON) {
|
|
}
|
|
if (status & INT4_TX_XOFF) {
|
|
}
|
|
if (status & INT4_RX_FIFO_OVRN) {
|
|
#if 0
|
|
if (sc->sc_psc->sc_swfree_min < MAX_RXMAPS) {
|
|
sc->sc_psc->sc_swfree_min++;
|
|
gmac_swfree_min_update(psc);
|
|
}
|
|
#endif
|
|
sc->sc_if.if_ierrors++;
|
|
}
|
|
if (status & INT4_RGMII_STSCHG) {
|
|
mii_tick(&sc->sc_mii);
|
|
}
|
|
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS, status);
|
|
|
|
if (do_ifstart)
|
|
gmc_ifstart(&sc->sc_if);
|
|
|
|
aprint_debug_dev(sc->sc_dev, "gmac_intr: sts=%#x/%#x/%#x/%#x/%#x\n",
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS),
|
|
bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS));
|
|
aprint_debug_dev(sc->sc_dev, "gmac_intr: exit rv=%d\n", rv);
|
|
return rv;
|
|
}
|
|
|
|
static int
|
|
gmc_match(device_t parent, cfdata_t cf, void *aux)
|
|
{
|
|
struct gmac_softc *psc = device_private(parent);
|
|
struct gmac_attach_args *gma = aux;
|
|
|
|
if ((unsigned int)gma->gma_phy > 31)
|
|
return 0;
|
|
if ((unsigned int)gma->gma_port > 1)
|
|
return 0;
|
|
if (gma->gma_intr < 1 || gma->gma_intr > 2)
|
|
return 0;
|
|
|
|
if (psc->sc_ports & (1 << gma->gma_port))
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void
|
|
gmc_attach(device_t parent, device_t self, void *aux)
|
|
{
|
|
struct gmac_softc * const psc = device_private(parent);
|
|
struct gmc_softc * const sc = device_private(self);
|
|
struct gmac_attach_args *gma = aux;
|
|
struct ifnet * const ifp = &sc->sc_if;
|
|
static const char eaddrs[2][6] = {
|
|
"\x0\x52\xc3\x11\x22\x33",
|
|
"\x0\x52\xc3\x44\x55\x66",
|
|
};
|
|
|
|
psc->sc_ports |= 1 << gma->gma_port;
|
|
sc->sc_port1 = (gma->gma_port == 1);
|
|
sc->sc_phy = gma->gma_phy;
|
|
|
|
sc->sc_dev = self;
|
|
sc->sc_psc = psc;
|
|
sc->sc_iot = psc->sc_iot;
|
|
sc->sc_ioh = psc->sc_ioh;
|
|
sc->sc_dmat = psc->sc_dmat;
|
|
|
|
bus_space_subregion(sc->sc_iot, sc->sc_ioh,
|
|
GMAC_PORTn_DMA_OFFSET(gma->gma_port), GMAC_PORTn_DMA_SIZE,
|
|
&sc->sc_dma_ioh);
|
|
bus_space_subregion(sc->sc_iot, sc->sc_ioh,
|
|
GMAC_PORTn_GMAC_OFFSET(gma->gma_port), GMAC_PORTn_GMAC_SIZE,
|
|
&sc->sc_gmac_ioh);
|
|
aprint_normal("\n");
|
|
aprint_naive("\n");
|
|
|
|
strlcpy(ifp->if_xname, device_xname(self), sizeof(ifp->if_xname));
|
|
ifp->if_flags = IFF_SIMPLEX|IFF_MULTICAST|IFF_BROADCAST;
|
|
ifp->if_softc = sc;
|
|
ifp->if_ioctl = gmc_ifioctl;
|
|
ifp->if_stop = gmc_ifstop;
|
|
ifp->if_start = gmc_ifstart;
|
|
ifp->if_init = gmc_ifinit;
|
|
|
|
IFQ_SET_READY(&ifp->if_snd);
|
|
|
|
sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU;
|
|
sc->sc_ec.ec_mii = &sc->sc_mii;
|
|
|
|
sc->sc_mii.mii_ifp = ifp;
|
|
sc->sc_mii.mii_statchg = gmc_mii_statchg;
|
|
sc->sc_mii.mii_readreg = gma->gma_mii_readreg;
|
|
sc->sc_mii.mii_writereg = gma->gma_mii_writereg;
|
|
|
|
ifmedia_init(&sc->sc_mii.mii_media, 0, gmc_mediachange,
|
|
gmc_mediastatus);
|
|
|
|
if_attach(ifp);
|
|
ether_ifattach(ifp, eaddrs[gma->gma_port]);
|
|
mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff,
|
|
gma->gma_phy, MII_OFFSET_ANY, 0);
|
|
|
|
if (LIST_EMPTY(&sc->sc_mii.mii_phys)) {
|
|
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
|
|
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
|
|
} else {
|
|
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
|
|
// ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX);
|
|
}
|
|
|
|
sc->sc_gmac_status = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh,
|
|
GMAC_STATUS);
|
|
sc->sc_gmac_sta_add[0] = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh,
|
|
GMAC_STA_ADD0);
|
|
sc->sc_gmac_sta_add[1] = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh,
|
|
GMAC_STA_ADD1);
|
|
sc->sc_gmac_sta_add[2] = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh,
|
|
GMAC_STA_ADD2);
|
|
sc->sc_gmac_mcast_filter[0] = bus_space_read_4(sc->sc_iot,
|
|
sc->sc_gmac_ioh, GMAC_MCAST_FILTER0);
|
|
sc->sc_gmac_mcast_filter[1] = bus_space_read_4(sc->sc_iot,
|
|
sc->sc_gmac_ioh, GMAC_MCAST_FILTER1);
|
|
sc->sc_gmac_rx_filter = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh,
|
|
GMAC_RX_FILTER);
|
|
sc->sc_gmac_config[0] = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh,
|
|
GMAC_CONFIG0);
|
|
sc->sc_dmavr = bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, GMAC_DMAVR);
|
|
|
|
/* sc->sc_int_enabled is already zeroed */
|
|
sc->sc_int_mask[0] = (sc->sc_port1 ? INT0_GMAC1 : INT0_GMAC0);
|
|
sc->sc_int_mask[1] = (sc->sc_port1 ? INT1_GMAC1 : INT1_GMAC0);
|
|
sc->sc_int_mask[2] = (sc->sc_port1 ? INT2_GMAC1 : INT2_GMAC0);
|
|
sc->sc_int_mask[3] = (sc->sc_port1 ? INT3_GMAC1 : INT3_GMAC0);
|
|
sc->sc_int_mask[4] = (sc->sc_port1 ? INT4_GMAC1 : INT4_GMAC0);
|
|
|
|
if (!sc->sc_port1) {
|
|
sc->sc_ih = intr_establish(gma->gma_intr, IPL_NET, IST_LEVEL_HIGH,
|
|
gmc_intr, sc);
|
|
KASSERT(sc->sc_ih != NULL);
|
|
}
|
|
|
|
callout_init(&sc->sc_mii_ch, 0);
|
|
callout_setfunc(&sc->sc_mii_ch, gmc_mii_tick, sc);
|
|
|
|
aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
|
|
ether_sprintf(CLLADDR(sc->sc_if.if_sadl)));
|
|
}
|
|
|
|
CFATTACH_DECL_NEW(gmc, sizeof(struct gmc_softc),
|
|
gmc_match, gmc_attach, NULL, NULL);
|