0d476cb7d0
machine-independent code for more sane access to bus resources.
Defines:
bus_{io,mem}_{map,unmap}
bus_{io,mem}_{read,write}_{1,2,4,8}
bus_io_{read,write}_multi_{1,2,4,8}
functions, and several types to go with them.
Note: The bus_io_*_8 functions are not supported.
122 lines
5.0 KiB
C
122 lines
5.0 KiB
C
/* $NetBSD: bus.h,v 1.1 1996/05/16 18:08:40 mark Exp $ */
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/*
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM32_BUS_H_
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#define _ARM32_BUS_H_
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/*
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* I/O addresses (in bus space)
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*/
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typedef u_long bus_io_addr_t;
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typedef u_long bus_io_size_t;
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/*
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* Memory addresses (in bus space)
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*/
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typedef u_long bus_mem_addr_t;
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typedef u_long bus_mem_size_t;
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/*
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* Access methods for bus resources, I/O space, and memory space.
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*/
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typedef void *bus_chipset_tag_t;
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typedef u_long bus_io_handle_t;
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typedef caddr_t bus_mem_handle_t;
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#define bus_io_map(t, port, size, iohp) ((void) t, *iohp = port, 0)
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#define bus_io_unmap(t, ioh, size)
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#define bus_io_read_1(t, h, o) ((void) t, (*(volatile u_int8_t *)((h) + (o))))
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#define bus_io_read_2(t, h, o) ((void) t, (*(volatile u_int16_t *)((h) + (o))))
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#define bus_io_read_4(t, h, o) ((void) t, (*(volatile u_int32_t *)((h) + (o))))
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#if 0 /* Cause a link error for bus_io_read_8 */
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#define bus_io_read_8(t, h, o) !!! bus_io_read_8 unimplemented !!!
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#endif
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#define bus_io_read_multi_1(t, h, o, a, c) \
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((void) t, insb((h) + (o), (a), (c)))
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#define bus_io_read_multi_2(t, h, o, a, c) \
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((void) t, insw((h) + (o), (a), (c)))
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#define bus_io_read_multi_4(t, h, o, a, c) \
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((void) t, insl((h) + (o), (a), (c)))
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#if 0 /* Cause a link error for bus_io_read_multi_8 */
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#define bus_io_read_multi_8(t, h, o, a, c) \
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!!! bus_io_read_multi_8 unimplemented !!!
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#endif
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#define bus_io_write_1(t, h, o, v) \
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((void) t, ((void)(*(volatile u_int8_t *)((h) + (o)) = (v))))
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#define bus_io_write_2(t, h, o, v) \
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((void) t, ((void)(*(volatile u_int16_t *)((h) + (o)) = (v))))
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#define bus_io_write_4(t, h, o, v) \
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((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))))
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#if 0 /* Cause a link error for bus_io_write_8 */
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#define bus_io_write_8(t, h, o, v) !!! bus_io_write_8 unimplemented !!!
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#endif
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#define bus_io_write_multi_1(t, h, o, a, c) \
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((void) t, outsb((h) + (o), (a), (c)))
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#define bus_io_write_multi_2(t, h, o, a, c) \
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((void) t, outsw((h) + (o), (a), (c)))
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#define bus_io_write_multi_4(t, h, o, a, c) \
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((void) t, outsl((h) + (o), (a), (c)))
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#if 0 /* Cause a link error for bus_io_write_multi_8 */
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#define bus_io_write_multi_8(t, h, o, a, c) \
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!!! bus_io_write_multi_8 unimplimented !!!
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#endif
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#if 1 /* */
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int bus_mem_map __P((bus_chipset_tag_t t, bus_mem_addr_t bpa,
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bus_mem_size_t size, int cacheable, bus_mem_handle_t *mhp));
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void bus_mem_unmap __P((bus_chipset_tag_t t, bus_mem_handle_t memh,
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bus_mem_size_t size));
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#else
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#define bus_mem_map(t, bpa, size, cacheable, mhp) ((void) t, *mhp = bpa, 0)
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#define bus_mem_unmap(t, memh, size)
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#endif
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#define bus_mem_read_1(t, h, o) ((void) t, (*(volatile u_int8_t *)((h) + (o))))
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#define bus_mem_read_2(t, h, o) ((void) t, (*(volatile u_int16_t *)((h) + (o))))
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#define bus_mem_read_4(t, h, o) ((void) t, (*(volatile u_int32_t *)((h) + (o))))
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#define bus_mem_read_8(t, h, o) ((void) t, (*(volatile u_int64_t *)((h) + (o))))
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#define bus_mem_write_1(t, h, o, v) \
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((void) t, ((void)(*(volatile u_int8_t *)((h) + (o)) = (v))))
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#define bus_mem_write_2(t, h, o, v) \
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((void) t, ((void)(*(volatile u_int16_t *)((h) + (o)) = (v))))
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#define bus_mem_write_4(t, h, o, v) \
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((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))))
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#define bus_mem_write_8(t, h, o, v) \
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((void) t, ((void)(*(volatile u_int64_t *)((h) + (o)) = (v))))
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#endif /* _ARM32_BUS_H_ */
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