445 lines
12 KiB
C
445 lines
12 KiB
C
/* $NetBSD: vrip.c,v 1.13 2002/01/02 13:13:21 uch Exp $ */
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/*-
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* Copyright (c) 1999
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* Shin Takemura and PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the PocketBSD project
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* and its contributors.
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* 4. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include "opt_vr41xx.h"
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#include "opt_tx39xx.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/reboot.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/autoconf.h>
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#include <machine/platid.h>
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#include <machine/platid_mask.h>
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#include <hpcmips/vr/vr.h>
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#include <hpcmips/vr/vrcpudef.h>
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#include <hpcmips/vr/vripreg.h>
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#include <hpcmips/vr/vripvar.h>
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#include <hpcmips/vr/icureg.h>
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#include "locators.h"
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#define VRIPDEBUG
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#ifdef VRIPDEBUG
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#ifndef VRIPDEBUG_CONF
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#define VRIPDEBUG_CONF 0
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#endif /* VRIPDEBUG_CONF */
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int vrip_debug = VRIPDEBUG_CONF;
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#define DPRINTF(arg) if (vrip_debug) printf arg;
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#define DBITDISP32(reg) if (vrip_debug) bitdisp32(reg);
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#define DDUMP_LEVEL2MASK(sc,arg) if (vrip_debug) vrip_dump_level2mask(sc,arg)
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#else
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#define DPRINTF(arg)
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#define DBITDISP32(arg)
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#define DDUMP_LEVEL2MASK(sc,arg)
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#endif
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int vripmatch(struct device *, struct cfdata *, void *);
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void vripattach(struct device *, struct device *, void *);
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int vrip_print(void *, const char *);
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int vrip_search(struct device *, struct cfdata *, void *);
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int vrip_intr(void *, u_int32_t, u_int32_t);
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static void vrip_dump_level2mask(vrip_chipset_tag_t, void *);
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struct cfattach vrip_ca = {
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sizeof(struct vrip_softc), vripmatch, vripattach
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};
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#define MAX_LEVEL1 32
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struct vrip_softc *the_vrip_sc = NULL;
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static struct intrhand {
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int (*ih_fun)(void *);
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void *ih_arg;
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int ih_l1line;
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int ih_ipl;
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bus_addr_t ih_lreg;
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bus_addr_t ih_mlreg;
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bus_addr_t ih_hreg;
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bus_addr_t ih_mhreg;
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} intrhand[MAX_LEVEL1] = {
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[VRIP_INTR_PIU] = { 0, 0, 0, 0, ICUPIUINT_REG_W,MPIUINT_REG_W },
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[VRIP_INTR_AIU] = { 0, 0, 0, 0, AIUINT_REG_W, MAIUINT_REG_W },
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[VRIP_INTR_KIU] = { 0, 0, 0, 0, KIUINT_REG_W, MKIUINT_REG_W },
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[VRIP_INTR_GIU] = { 0, 0, 0, 0, GIUINT_L_REG_W, MGIUINT_L_REG_W,
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GIUINT_H_REG_W, MGIUINT_H_REG_W },
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[VRIP_INTR_FIR] = { 0, 0, 0, 0, FIRINT_REG_W, MFIRINT_REG_W },
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[VRIP_INTR_DSIU] = { 0, 0, 0, 0, DSIUINT_REG_W, MDSIUINT_REG_W },
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[VRIP_INTR_PCI] = { 0, 0, 0, 0, PCIINT_REG_W, MPCIINT_REG_W },
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[VRIP_INTR_SCU] = { 0, 0, 0, 0, SCUINT_REG_W, MSCUINT_REG_W },
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[VRIP_INTR_CSI] = { 0, 0, 0, 0, CSIINT_REG_W, MCSIINT_REG_W },
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[VRIP_INTR_BCU] = { 0, 0, 0, 0, BCUINT_REG_W, MBCUINT_REG_W }
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};
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#define LEGAL_LEVEL1(x) ((x) >= 0 && (x) < MAX_LEVEL1)
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void
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bitdisp16(u_int16_t a)
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{
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u_int16_t j;
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for (j = 0x8000; j > 0; j >>=1)
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printf ("%c", a&j ?'|':'.');
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printf ("\n");
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}
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void
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bitdisp32(u_int32_t a)
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{
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u_int32_t j;
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for (j = 0x80000000; j > 0; j >>=1)
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printf ("%c" , a&j ? '|' : '.');
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printf ("\n");
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}
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void
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bitdisp64(u_int32_t a[2])
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{
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u_int32_t j;
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for( j = 0x80000000 ; j > 0 ; j >>=1 )
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printf("%c" , a[1]&j ?';':',' );
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for( j = 0x80000000 ; j > 0 ; j >>=1 )
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printf("%c" , a[0]&j ?'|':'.' );
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printf("\n");
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}
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int
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vripmatch(struct device *parent, struct cfdata *match, void *aux)
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{
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struct mainbus_attach_args *ma = aux;
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#ifdef TX39XX
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if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX))
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return (0);
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#endif /* TX39XX */
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if (strcmp(ma->ma_name, match->cf_driver->cd_name))
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return (0);
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return (1);
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}
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void
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vripattach(struct device *parent, struct device *self, void *aux)
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{
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struct mainbus_attach_args *ma = aux;
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struct vrip_softc *sc = (struct vrip_softc*)self;
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printf("\n");
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/*
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* Map ICU (Interrupt Control Unit) register space.
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*/
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sc->sc_iot = ma->ma_iot;
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if (bus_space_map(sc->sc_iot, VRIP_ICU_ADDR,
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0x20 /*XXX lower area only*/,
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0, /* no flags */
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&sc->sc_ioh)) {
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printf("vripattach: can't map ICU register.\n");
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return;
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}
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/*
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* Disable all Level 1 interrupts.
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*/
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sc->sc_intrmask = 0;
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000);
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT2_REG_W, 0x0000);
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/*
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* Level 1 interrupts are redirected to HwInt0
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*/
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vr_intr_establish(VR_INTR0, vrip_intr, self);
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the_vrip_sc = sc;
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/*
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* Attach each devices
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* GIU CMU interface interface is used by other system device.
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* so attach first
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*/
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sc->sc_pri = 2;
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config_search(vrip_search, self, vrip_print);
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/* Other system devices. */
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sc->sc_pri = 1;
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config_search(vrip_search, self, vrip_print);
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}
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int
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vrip_print(void *aux, const char *hoge)
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{
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struct vrip_attach_args *va = (struct vrip_attach_args*)aux;
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if (va->va_addr)
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printf(" addr 0x%lx", va->va_addr);
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if (va->va_size > 1)
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printf("-0x%lx", va->va_addr + va->va_size - 1);
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if (va->va_intr != VRIPCF_INTR_DEFAULT)
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printf(" intr %d", va->va_intr);
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return (UNCONF);
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}
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int
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vrip_search(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct vrip_softc *sc = (struct vrip_softc *)parent;
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struct vrip_attach_args va;
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va.va_vc = sc;
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va.va_iot = sc->sc_iot;
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va.va_addr = cf->cf_loc[VRIPCF_ADDR];
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va.va_size = cf->cf_loc[VRIPCF_SIZE];
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va.va_intr = cf->cf_loc[VRIPCF_INTR];
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va.va_addr2 = cf->cf_loc[VRIPCF_ADDR2];
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va.va_size2 = cf->cf_loc[VRIPCF_SIZE2];
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va.va_gpio_chips = sc->sc_gpio_chips;
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va.va_cc = sc->sc_cc;
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va.va_cf = sc->sc_cf;
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if (((*cf->cf_attach->ca_match)(parent, cf, &va) == sc->sc_pri))
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config_attach(parent, cf, &va, vrip_print);
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return (0);
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}
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void *
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vrip_intr_establish(vrip_chipset_tag_t vc, int intr, int level,
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int (*ih_fun)(void *), void *ih_arg)
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{
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struct intrhand *ih;
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if (!LEGAL_LEVEL1(intr))
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return (0);
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ih = &intrhand[intr];
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if (ih->ih_fun) /* Can't share level 1 interrupt */
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return (0);
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ih->ih_l1line = intr;
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ih->ih_fun = ih_fun;
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ih->ih_arg = ih_arg;
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/* Mask level 2 interrupt mask register. (disable interrupt) */
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vrip_intr_setmask2(vc, ih, ~0, 0);
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/* Unmask Level 1 interrupt mask register (enable interrupt) */
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vrip_intr_setmask1(vc, ih, 1);
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return ((void *)ih);
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}
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void
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vrip_intr_disestablish(vrip_chipset_tag_t vc, void *arg)
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{
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struct intrhand *ih = arg;
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ih->ih_fun = NULL;
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ih->ih_arg = NULL;
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/* Mask level 2 interrupt mask register(if any). (disable interrupt) */
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vrip_intr_setmask2(vc, ih, ~0, 0);
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/* Mask Level 1 interrupt mask register (disable interrupt) */
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vrip_intr_setmask1(vc, ih, 0);
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}
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void
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vrip_intr_suspend()
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{
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bus_space_tag_t iot = the_vrip_sc->sc_iot;
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bus_space_handle_t ioh = the_vrip_sc->sc_ioh;
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bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER));
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bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, 0);
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}
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void
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vrip_intr_resume()
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{
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u_int32_t reg = the_vrip_sc->sc_intrmask;
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bus_space_tag_t iot = the_vrip_sc->sc_iot;
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bus_space_handle_t ioh = the_vrip_sc->sc_ioh;
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bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff);
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bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff);
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}
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/* Set level 1 interrupt mask. */
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void
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vrip_intr_setmask1(vrip_chipset_tag_t vc, void *arg, int enable)
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{
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struct vrip_softc *sc = (void*)vc;
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struct intrhand *ih = arg;
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int level1 = ih->ih_l1line;
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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u_int32_t reg = sc->sc_intrmask;
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reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) |
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((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000);
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if (enable)
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reg |= (1 << level1);
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else {
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reg &= ~(1 << level1);
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}
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sc->sc_intrmask = reg;
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bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff);
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bus_space_write_2 (iot, ioh, MSYSINT2_REG_W, (reg >> 16) & 0xffff);
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DBITDISP32(reg);
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return;
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}
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static void
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vrip_dump_level2mask(vrip_chipset_tag_t vc, void *arg)
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{
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struct vrip_softc *sc = (void*)vc;
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struct intrhand *ih = arg;
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u_int32_t reg;
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if (ih->ih_mlreg) {
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printf ("level1[%d] level2 mask:", ih->ih_l1line);
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reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg);
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if (ih->ih_mhreg) { /* GIU [16:31] case only */
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reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mhreg) << 16);
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bitdisp32(reg);
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} else
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bitdisp16(reg);
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}
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}
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/* Get level 2 interrupt status */
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void
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vrip_intr_get_status2(vrip_chipset_tag_t vc, void *arg,
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u_int32_t *mask /* Level 2 mask */)
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{
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struct vrip_softc *sc = (void*)vc;
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struct intrhand *ih = arg;
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u_int32_t reg;
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reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
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ih->ih_lreg);
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reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh,
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ih->ih_hreg) << 16)&0xffff0000);
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/* bitdisp32(reg);*/
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*mask = reg;
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}
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/* Set level 2 interrupt mask. */
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void
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vrip_intr_setmask2(vrip_chipset_tag_t vc, void *arg,
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u_int32_t mask /* Level 2 mask */, int onoff)
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{
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struct vrip_softc *sc = (void*)vc;
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struct intrhand *ih = arg;
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u_int16_t reg;
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DPRINTF(("vrip_intr_setmask2:\n"));
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DDUMP_LEVEL2MASK(vc, arg);
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#ifdef WINCE_DEFAULT_SETTING
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#warning WINCE_DEFAULT_SETTING
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#else
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if (ih->ih_mlreg) {
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reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg);
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if (onoff)
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reg |= (mask&0xffff);
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else
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reg &= ~(mask&0xffff);
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, ih->ih_mlreg, reg);
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if (ih->ih_mhreg != -1) { /* GIU [16:31] case only */
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reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
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ih->ih_mhreg);
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if (onoff)
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reg |= ((mask >> 16) & 0xffff);
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else
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reg &= ~((mask >> 16) & 0xffff);
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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ih->ih_mhreg, reg);
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}
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}
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#endif /* WINCE_DEFAULT_SETTING */
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DDUMP_LEVEL2MASK(vc, arg);
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return;
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}
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int
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vrip_intr(void *arg, u_int32_t pc, u_int32_t statusReg)
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{
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struct vrip_softc *sc = (struct vrip_softc*)arg;
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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int i;
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u_int32_t reg, mask;
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/*
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* Read level1 interrupt status.
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*/
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reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) |
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((bus_space_read_2 (iot, ioh, SYSINT2_REG_W)<< 16)&0xffff0000);
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mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) |
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((bus_space_read_2 (iot, ioh, MSYSINT2_REG_W)<< 16)&0xffff0000);
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reg &= mask;
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/*
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* Dispatch each handler.
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*/
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for (i = 0; i < 32; i++) {
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register struct intrhand *ih = &intrhand[i];
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if (ih->ih_fun && (reg & (1 << i))) {
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ih->ih_fun(ih->ih_arg);
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}
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}
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return (1);
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}
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void
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vrip_cmu_function_register(vrip_chipset_tag_t vc, vrcmu_function_tag_t func,
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vrcmu_chipset_tag_t arg)
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{
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struct vrip_softc *sc = (void*)vc;
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sc->sc_cf = func;
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sc->sc_cc = arg;
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}
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void
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vrip_gpio_register(vrip_chipset_tag_t vc, hpcio_chip_t chip)
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{
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struct vrip_softc *sc = (void*)vc;
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if (chip->hc_chipid < 0 || VRIP_NIOCHIPS <= chip->hc_chipid)
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panic("%s: '%s' has unknown id, %d", __FUNCTION__,
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chip->hc_name, chip->hc_chipid);
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sc->sc_gpio_chips[chip->hc_chipid] = chip;
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}
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