8927d6f1be
to be cleared always in edmcadone(), otherwise if there is a write via bounce buffer followed by read directly to buf, the read operation would return trashed data (the buf data would get overwritten by contents of bounce buffer in edmcadone()). Reset b_resid as necessary when the i/o is done, too. g/c some unneeded stuff, use lockmgr()-style locking in ed_[un]lock(), better avoid some deadlocks These changes make the driver quite a bit more stable. It's actually reliable enough to be possible to newfs the drive and use it for read/write filesystem now.
133 lines
4.7 KiB
C
133 lines
4.7 KiB
C
/* $NetBSD: edcreg.h,v 1.2 2001/04/22 11:32:49 jdolecek Exp $ */
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/*
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jaromir Dolecek.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for MCA ESDI controllers and disks.
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*/
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#define ESDIC_IOPRM 0x3510
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#define ESDIC_IOALT 0x3518
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#define ESDIC_REG_NPORTS 8
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#define ESDIC_IRQ 14 /* this is fixed */
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/* pos2 */
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#define IO_IS_ALT 0x02
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#define DRQ_MASK 0x3c
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#define FAIRNESS_ENABLE 0x40
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/* pos3 */
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#define PACING_INT_MASK 0x30
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/* pos4 */
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#define PACING_CTRL_DISABLE 0x01
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#define RELEASE_2 0x02 /* lower bit of Time to Release */
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#define RELEASE_1 0x04 /* higher bit of Time to Release */
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/* controller registers */
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#define SIFR 0 /* read Status Interface Register,
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2 bytes, little endian */
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#define SIFR_CMD_MASK 0x2f
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#define CIFR 0 /* write - Command Interface Reg,
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2 bytes, little endian */
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#define CIFR_LONG_CMD (1<<14) /* 4 word command */
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/* Command Codes */
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#define CMD_READ_DATA 0x01 /* uses DMA */
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#define CMD_WRITE_DATA 0x02 /* uses DMA */
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#define CMD_READ_VERIFY 0x03
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#define CMD_WRITE_VERIFY 0x04 /* uses DMA */
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#define CMD_SEEK 0x05
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#define CMD_PARK_HEAD 0x06
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#define CMD_GET_CMD_COMP_STATUS 0x07
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#define CMD_GET_DEV_STATUS 0x08
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#define CMD_GET_DEV_CONF 0x09
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#define CMD_GET_POS_INFO 0x0A
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#define CMD_TRANSLATE_RBA 0x0B
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#define CMD_WRITE_ATTACH_BUFF 0x10 /* uses DMA */
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#define CMD_READ_ATTACH_BUFF 0x11 /* uses DMA */
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#define CMD_RUN_DIAG_TEST 0x12
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#define CMD_GET_DIAG_STAT_BLOCK 0x14
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#define CMD_GET_MFG_HEADER 0x15 /* uses DMA */
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#define CMD_FORMAT_UNIT 0x16 /* uses DMA */
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#define CMD_FORMAT_PREPARE 0x17
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#define CMD_SET_MAX_RBA 0x1A
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#define CMD_SET_PWR_SAV_MODE 0x1B /* optional */
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#define CMD_POWER_CONS_CMD 0x1C /* optional */
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#define BCR 2 /* write */
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#define BCR_INT_ENABLE 0x01
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#define BCR_DMA_ENABLE 0x02
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#define BCR_RESET 0x80
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#define BSR 2 /* read */
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#define BSR_DMA_ENABLED 0x80
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#define BSR_INT_PENDING 0x40
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#define BSR_CMD_INPROGRESS 0x20
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#define BSR_BUSY 0x10
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#define BSR_SIFR_FULL 0x08 /* also called STATUS OUT */
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#define BSR_CIFR_FULL 0x04
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#define BSR_TRANSFER_REQ 0x02
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#define BSR_INTR 0x01
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#define ISR 3 /* read, Interrupt Status Register */
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#define ISR_DEV_SELECT_MASK 0xE0
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#define ISR_ATTACH_ERR 0x10
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#define ISR_INTR_ID_MASK 0x0F
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#define ISR_COMPLETED 0x01
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#define ISR_COMPLETED_WITH_ECC 0x03
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#define ISR_COMPLETED_RETRIES 0x05
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#define ISR_PARTIAL_FORMAT 0x06 /* Status available */
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#define ISR_COMPLETED_WARNING 0x08
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#define ISR_ABORT_COMPLETED 0x09
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#define ISR_RESET_COMPLETED 0x0A
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#define ISR_DATA_TRANSFER_RDY 0x0B /* No Status Block */
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#define ISR_CMD_FAILED 0x0C
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#define ISR_DMA_ERROR 0x0D
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#define ISR_CMD_BLOCK_ERROR 0x0E
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#define ISR_ATTN_ERROR 0x0F
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/* Macros to get info from command status block */
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#define SB_GET_CMD_STATUS(sb) (((sb)[1] & 0xff00) >> 8)
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#define SB_RESBLKCNT_IDX 3
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#define ATN 3 /* write, Attention register */
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#define ATN_CMD_REQ 1
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#define ATN_END_INT 2 /* End of Interrupt (EOI) */
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#define ATN_ABORT_CMD 3
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#define ATN_RESET_ATTACHMENT 4
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#define DASD_DEVNO_CONTROLLER 7 /* Device number for controller */
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