353 lines
14 KiB
C
353 lines
14 KiB
C
/* $NetBSD: mc68851.h,v 1.3 1997/01/23 22:15:41 gwr Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jeremy Cooper.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file should contain the machine-independent definitions
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* related to the Motorola MC68881 Memory Management Unit (MMU).
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* Things that depend on the contents of the Translation Control
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* (TC) register should be in <machine/pte.h>, not here.
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*/
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#ifndef _SUN3X_MC68851_H
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#define _SUN3X_MC68851_H
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/**************************** MMU STRUCTURES ****************************
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* MMU structures define the format of data used by the MC68851. *
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************************************************************************
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* A virtual address is translated into a physical address by dividing its
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* bits into four fields. The first three fields are used as indexes into
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* descriptor tables and the last field (the 13 lowest significant
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* bits) is an offset to be added to the base address found at the final
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* table. The first three fields are named TIA, TIB and TIC respectively.
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* 31 12 0
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* +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+
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* | TIA | TIB | TIC | OFFSET |
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* +-.-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-+-.-.-.-.-.-.-.-.-.-.-.-.-+
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*/
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#define MMU_TIA_SHIFT (13+6+6)
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#define MMU_TIA_MASK (0xfe000000)
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#define MMU_TIA_RANGE (0x02000000)
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#define MMU_TIB_SHIFT (13+6)
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#define MMU_TIB_MASK (0x01f80000)
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#define MMU_TIB_RANGE (0x00080000)
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#define MMU_TIC_SHIFT (13)
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#define MMU_TIC_MASK (0x0007e000)
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#define MMU_TIC_RANGE (0x00002000)
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#define MMU_PAGE_SHIFT (13)
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#define MMU_PAGE_MASK (0xffffe000)
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#define MMU_PAGE_SIZE (0x00002000)
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/* Macros which extract each of these fields out of a given
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* VA.
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*/
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#define MMU_TIA(va) \
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((unsigned long) ((va) & MMU_TIA_MASK) >> MMU_TIA_SHIFT)
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#define MMU_TIB(va) \
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((unsigned long) ((va) & MMU_TIB_MASK) >> MMU_TIB_SHIFT)
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#define MMU_TIC(va) \
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((unsigned long) ((va) & MMU_TIC_MASK) >> MMU_TIC_SHIFT)
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/* The widths of the TIA, TIB, and TIC fields determine the size (in
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* elements) of the tables they index.
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*/
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#define MMU_A_TBL_SIZE (128)
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#define MMU_B_TBL_SIZE (64)
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#define MMU_C_TBL_SIZE (64)
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/* Rounding macros.
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* The MMU_ROUND macros are named misleadingly. MMU_ROUND_A actually
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* rounds an address to the nearest B table boundary, and so on.
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* MMU_ROUND_C() is synonmous with sun3x_round_page().
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*/
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#define MMU_ROUND_A(pa)\
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((unsigned long) (pa) & MMU_TIA_MASK)
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#define MMU_ROUND_UP_A(pa)\
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((unsigned long) (pa + MMU_TIA_RANGE - 1) & MMU_TIA_MASK)
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#define MMU_ROUND_B(pa)\
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((unsigned long) (pa) & (MMU_TIA_MASK|MMU_TIB_MASK))
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#define MMU_ROUND_UP_B(pa)\
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((unsigned long) (pa + MMU_TIB_RANGE - 1) & (MMU_TIA_MASK|MMU_TIB_MASK))
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#define MMU_ROUND_C(pa)\
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((unsigned long) (pa) & MMU_PAGE_MASK)
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#define MMU_ROUND_UP_C(pa)\
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((unsigned long) (pa + MMU_PAGE_SIZE - 1) & MMU_PAGE_MASK)
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/** MC68851 Root Pointer
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* All address translations begin with the examination of the value
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* in the MC68851 Root Pointer register. It describes the base address
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* (in physical memory) of the root table to be used as well as any limits
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* to the address range it supports. Its structure is identical to a Long
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* Format Table Descriptor (described below.)
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*/
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struct mmu_rootptr {
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u_long rp_attr; /* Lower/Upper Limit and access flags */
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u_long rp_addr; /* Physical Base Address */
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};
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typedef struct mmu_rootptr mmu_rootptr_t;
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/** MC68851 Long Format Table Descriptor
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* The root table for a sun3x pmap is a 128 element array of 'long format
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* table descriptors'. The structure of a long format table descriptor is:
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*
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* 63 48
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* +---+---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
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* |L/U| LIMIT |
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* +---+---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
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* | RAL | WAL |SG | S | 0 | 0 | 0 | 0 | U |WP |DT (10)|
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* +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
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* | TABLE PHYSICAL ADDRESS (BITS 31-16) |
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* +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+
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* | TABLE PHYSICAL ADDRESS (15-4) | UNUSED |
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* +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+
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* 15 0
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*
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* Note: keep the unused bits set to zero so that no masking of the
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* base address is needed.
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*/
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struct mmu_long_dte_struct { /* 'dte' stands for 'descriptor table entry' */
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union {
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struct {
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char lu_flag:1; /* Lower/Upper Limit flag */
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int limit:15; /* Table Size limit */
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char ral:3; /* Read Access Level */
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char wal:3; /* Write Access Level */
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char sg:1; /* Shared Globally flag */
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char supv:1; /* Supervisor Only flag */
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char rsvd:4; /* Reserved (All zeros) */
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char u:1; /* Used flag */
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char wp:1; /* Write Protect flag */
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char dt:2; /* Descriptor Type */
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/* Bit masks for fields above */
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#define MMU_LONG_DTE_LU 0x80000000
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#define MMU_LONG_DTE_LIMIT 0x7fff0000
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#define MMU_LONG_DTE_RAL 0x0000e000
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#define MMU_LONG_DTE_WAL 0x00001c00
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#define MMU_LONG_DTE_SG 0x00000200
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#define MMU_LONG_DTE_SUPV 0x00000100
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#define MMU_LONG_DTE_USED 0x00000008
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#define MMU_LONG_DTE_WP 0x00000004
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#define MMU_LONG_DTE_DT 0x00000003
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} attr_struct;
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u_long raw; /* struct above, addressable as a long */
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} attr;
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union {
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struct {
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int base_addr:28; /* Physical base address
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char unused:4; * of the table pointed to
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* by this entry.
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*/
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/* Bit masks for fields above */
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#define MMU_LONG_DTE_BASEADDR 0xfffffff0
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} addr_struct;
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u_long raw; /* struct above, addressable as a long */
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} addr;
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};
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typedef struct mmu_long_dte_struct mmu_long_dte_t;
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typedef struct mmu_long_dte_struct *mmu_long_dtbl_t;
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/** MC68851 Long Format Page Descriptor
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* Although not likely to be used in this implementation, a level
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* 'A' table may contain long format PAGE descriptors. A long format
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* page descriptor is the same size as a long format table descriptor.
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* Its discriminating feature to the MMU is its descriptor field: 01.
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* 63 48
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* +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
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* | UNUSED |
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* +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
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* | RAL | WAL |SG | S | G |CI | L | M | U |WP |DT (01)|
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* +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+
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* | TABLE PHYSICAL ADDRESS (BITS 31-16) |
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* +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
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* |TABLE PHYS. ADDRESS (15-8) | UNUSED |
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* +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
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* 15 0
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*/
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struct mmu_long_pte_struct { /* 'pte' stands for 'page table entry' */
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union {
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struct {
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int unused:16; /* Unused */
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char ral:3; /* Read Access Level */
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char wal:3; /* Write Access Level */
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char sg:1; /* Shared Globally flag */
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char supv:1; /* Supervisor Only flag */
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char g:1; /* Gate allowed */
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char ci:1; /* Cache inhibit */
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char l:1; /* Lock entry */
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char m:1; /* Modified flag */
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char u:1; /* Used flag */
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char wp:1; /* Write Protect flag */
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char dt:2; /* Descriptor Type */
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/* Bit masks for fields above */
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#define MMU_LONG_PTE_RAL 0x0000e000
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#define MMU_LONG_PTE_WAL 0x00001c00
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#define MMU_LONG_PTE_SG 0x00000200
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#define MMU_LONG_PTE_SUPV 0x00000100
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#define MMU_LONG_PTE_GATE 0x00000080
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#define MMU_LONG_PTE_CI 0x00000040
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#define MMU_LONG_PTE_LOCK 0x00000020
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#define MMU_LONG_PTE_M 0x00000010
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#define MMU_LONG_PTE_USED 0x00000008
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#define MMU_LONG_PTE_WP 0x00000004
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#define MMU_LONG_PTE_DT 0x00000003
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} attr_struct;
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u_long raw; /* struct above, addressable as a long */
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} attr;
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union {
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struct {
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long base_addr:24; /* Physical base address
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char unused:8; * of page this entry
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* points to.
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*/
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/* Bit masks for fields above */
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#define MMU_LONG_PTE_BASEADDR 0xffffff00
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} addr_struct;
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u_long raw; /* struct above, addressable as a long */
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} addr;
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};
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typedef struct mmu_long_pte_struct mmu_long_pte_t;
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typedef struct mmu_long_pte_struct *mmu_long_ptbl_t;
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/* Every entry in the level A table (except for the page entries
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* described above) points to a level B table. Level B tables are
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* arrays of 'short format' table descriptors. Their structure
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* is smaller than an A table descriptor and is as follows:
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*
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* 31 16
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* +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
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* | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) |
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* +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+
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* | TABLE PHYSICAL BASE ADDRESS (15-4) | U |WP |DT (10)|
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* +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+
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* 15 0
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*/
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struct mmu_short_dte_struct { /* 'dte' stands for 'descriptor table entry' */
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union {
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struct {
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long base_addr:28;
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char u:1;
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char wp:1;
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char dt:2;
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#define MMU_SHORT_DTE_BASEADDR 0xfffffff0
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#define MMU_SHORT_DTE_USED 0x00000008
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#define MMU_SHORT_DTE_WP 0x00000004
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#define MMU_SHORT_DTE_DT 0x00000003
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} attr_struct;
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u_long raw;
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} attr;
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};
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typedef struct mmu_short_dte_struct mmu_short_dte_t;
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typedef struct mmu_short_dte_struct *mmu_short_dtbl_t;
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/* Every entry in a level B table points to a level C table. Level C tables
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* contain arrays of short format page 'entry' descriptors. A short format
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* page 'entry' is the same size as a short format page 'table'
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* descriptor (a B table entry). Thus B and C tables can be allocated
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* interchangeably from the same pool. However, we will keep them separate.
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*
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* The descriptor type (DT) field of a Page Table Entry (PTE) is '01'. This
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* indicates to the MMU that the address contained in the PTE's 'base
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* address' field is the base address for a physical page in memory to which
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* the VA should be mapped, and not a base address for a yet another
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* descriptor table, thus ending the table walk.
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*
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* 31 16
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* +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+
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* | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) |
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* +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+
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* |TABLE PHYS. BASE ADDRESS (15-8)| G |CI | L | M | U |WP |DT (10)|
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* +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+
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* 15 0
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*/
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struct mmu_short_pte_struct { /* 'pte' stands for 'page table entry' */
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union {
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struct {
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long base_addr:24;
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char g:1;
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char ci:1;
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char l:1;
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char m:1;
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char u:1;
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char wp:1;
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char dt:2;
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#define MMU_SHORT_PTE_BASEADDR 0xffffff00
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#define MMU_SHORT_PTE_UN2 0x00000080
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#define MMU_SHORT_PTE_CI 0x00000040
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#define MMU_SHORT_PTE_UN1 0x00000020
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#define MMU_SHORT_PTE_M 0x00000010
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#define MMU_SHORT_PTE_USED 0x00000008
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#define MMU_SHORT_PTE_WP 0x00000004
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#define MMU_SHORT_PTE_DT 0x00000003
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} attr_struct;
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u_long raw;
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} attr;
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};
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typedef struct mmu_short_pte_struct mmu_short_pte_t;
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typedef struct mmu_short_pte_struct *mmu_short_ptbl_t;
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/* These are bit masks and other values that are common to all types of
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* descriptors.
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*/
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/* Page table descriptors have a 'Descriptor Type' field describing the
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* format of the tables they point to. It is two bits wide and is one of:
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*/
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#define MMU_DT_INVALID 0x0 /* Invalid descriptor entry */
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#define MMU_DT_PAGE 0x1 /* Descriptor describes a page entry */
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#define MMU_DT_SHORT 0x2 /* describes a short format table */
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#define MMU_DT_LONG 0x3 /* describes a long format table */
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#define MMU_DT_MASK 0x00000003 /* Bit location of the DT field */
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/* Various macros for manipulating and setting MMU descriptor
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* characteristics.
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*/
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/* returns true if a descriptor is valid. */
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#define MMU_VALID_DT(dte) ((dte).attr.raw & MMU_DT_MASK)
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/* returns true if a descriptor is invalid */
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#define MMU_INVALID_DT(dte) (!((dte).attr.raw & MMU_DT_MASK))
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/* returns true if a descriptor has been referenced */
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#define MMU_PTE_USED(pte) ((pte).attr.raw & MMU_SHORT_PTE_USED)
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/* returns true if a descriptor has been modified */
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#define MMU_PTE_MODIFIED(pte) ((pte).attr.raw & MMU_SHORT_PTE_M)
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/* extracts the physical address from a pte */
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#define MMU_PTE_PA(pte) ((pte).attr.raw & MMU_SHORT_PTE_BASEADDR)
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/* extracts the physical address from a dte */
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#define MMU_DTE_PA(dte) ((dte).attr.raw & MMU_SHORT_DTE_BASEADDR)
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#endif /* _SUN3X_MC68851_H */
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