6a29394250
The MI softint(9) handles it in the kernel threads nowadays. Note "Emulation of VAX REI instruction" is still there to handle ASTs.
137 lines
3.7 KiB
C
137 lines
3.7 KiB
C
/* $NetBSD: intr.h,v 1.32 2008/12/21 17:42:05 tsutsui Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HP300_INTR_H_
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#define _HP300_INTR_H_
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#include <sys/device.h>
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#include <sys/queue.h>
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#include <machine/psl.h>
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/*
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* Interrupt "levels". These are a more abstract representation
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* of interrupt levels, and do not have the same meaning as m68k
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* CPU interrupt levels. They serve the following purposes:
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*
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* - properly order ISRs in the list for that CPU ipl
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* - compute CPU PSL values for the spl*() calls.
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* - used to create cookie for the splraiseipl().
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*/
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#define IPL_NONE 0
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#define IPL_SOFTCLOCK 1
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#define IPL_SOFTBIO 2
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#define IPL_SOFTNET 3
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#define IPL_SOFTSERIAL 4
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#define IPL_VM 5
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#define IPL_SCHED 6
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#define IPL_HIGH 7
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#define NIPL 8
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/*
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* Convert PSL values to m68k CPU IPLs and vice-versa.
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* Note: CPU IPL values are different from IPL_* used by splraiseipl().
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*/
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#define PSLTOIPL(x) (((x) >> 8) & 0xf)
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#define IPLTOPSL(x) ((((x) & 0xf) << 8) | PSL_S)
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extern int idepth;
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static inline bool
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cpu_intr_p(void)
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{
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return idepth != 0;
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}
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extern const uint16_t ipl2psl_table[NIPL];
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typedef int ipl_t;
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typedef struct {
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uint16_t _psl;
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} ipl_cookie_t;
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static inline ipl_cookie_t
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makeiplcookie(ipl_t ipl)
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{
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return (ipl_cookie_t){._psl = ipl2psl_table[ipl]};
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}
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static inline int
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splraiseipl(ipl_cookie_t icookie)
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{
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return _splraise(icookie._psl);
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}
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static inline void
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splx(int sr)
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{
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__asm volatile("movew %0,%%sr" : : "di" (sr));
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}
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/* These spl calls are _not_ to be used by machine-independent code. */
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#define splhil() splraise1()
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#define splkbd() splhil()
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/* These spl calls are used by machine-independent code. */
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#define spl0() _spl0()
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#define splsoftbio() splraise1()
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#define splsoftclock() splraise1()
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#define splsoftnet() splraise1()
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#define splsoftserial() splraise1()
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#define splvm() splraise5()
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#define splsched() spl6()
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#define splhigh() spl7()
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struct hp300_intrhand {
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LIST_ENTRY(hp300_intrhand) ih_q;
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int (*ih_fn)(void *);
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void *ih_arg;
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int ih_ipl;
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int ih_priority;
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};
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struct hp300_intr {
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LIST_HEAD(, hp300_intrhand) hi_q;
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struct evcnt hi_evcnt;
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};
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/* intr.c */
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void intr_init(void);
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void *intr_establish(int (*)(void *), void *, int, int);
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void intr_disestablish(void *);
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void intr_dispatch(int);
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#endif /* _HP300_INTR_H_ */
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