briggs 7f9445d14a It is best to allow a little time for the reset to settle in before ... we start polling the BMCR again. Greg Woods noted on tech-net@ that the DP83840A manual states that there should be a 500us delay between asserting software reset and attempting MII serial operations. I've also noted that a DP83815 can get into a bad state on cable removal and reinsertion if we do not delay here. This may well address PR/16346, and I seem to recall occasional reports of auto-negotiation and flaky kinds of errors that this might also alleviate.		2003-09-10 05:25:22 +00:00
..
acphy.c
acphyreg.h
amhphy.c
amhphyreg.h
bmtphy.c
bmtphyreg.h
brgphy.c
brgphyreg.h
devlist2h.awk
dmphy.c
dmphyreg.h
exphy.c
files.mii
gentbi.c
glxtphy.c
glxtphyreg.h
gphyter.c
gphyterreg.h
icsphy.c
icsphyreg.h
inphy.c
inphyreg.h
iophy.c
iophyreg.h
lxtphy.c
lxtphyreg.h
Makefile.miidevs
makphy.c
makphyreg.h
mii_bitbang.c
mii_bitbang.h
mii_physubr.c
mii.c
mii.h
miidevs
miidevs_data.h
miidevs.h
miivar.h
nsphy.c
nsphyreg.h
nsphyter.c
nsphyterreg.h
pnaphy.c
qsphy.c
qsphyreg.h
sqphy.c
sqphyreg.h
tlphy.c
tlphyreg.h
tlphyvar.h
tqphy.c
tqphyreg.h
ukphy_subr.c
ukphy.c
urlphy.c
urlphyreg.h