76c6161871
from FreeBSD/OpenBSD that supersedes ral*.[ch]. Not yet enabled because I don't have a CardBus controller to test and it will most likely crash during detach. I tried to include our modifications, but if something is missing please tell me or add it. Special thanks to minipci.biz for the donation of one PCI RT2661 and one CardBus RT2661.
338 lines
9.9 KiB
C
338 lines
9.9 KiB
C
/* $OpenBSD: rt2661reg.h,v 1.5 2006/01/14 12:43:27 damien Exp $ */
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/*-
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* Copyright (c) 2006
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* Damien Bergamini <damien.bergamini@free.fr>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#define RT2661_TX_RING_COUNT 32
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#define RT2661_MGT_RING_COUNT 32
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#define RT2661_RX_RING_COUNT 64
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#define RT2661_TX_DESC_SIZE (sizeof (struct rt2661_tx_desc))
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#define RT2661_TX_DESC_WSIZE (RT2661_TX_DESC_SIZE / 4)
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#define RT2661_RX_DESC_SIZE (sizeof (struct rt2661_rx_desc))
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#define RT2661_RX_DESC_WSIZE (RT2661_RX_DESC_SIZE / 4)
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#define RT2661_MAX_SCATTER 5
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/*
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* Control and status registers.
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*/
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#define RT2661_HOST_CMD_CSR 0x0008
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#define RT2661_MCU_CNTL_CSR 0x000c
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#define RT2661_SOFT_RESET_CSR 0x0010
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#define RT2661_MCU_INT_SOURCE_CSR 0x0014
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#define RT2661_MCU_INT_MASK_CSR 0x0018
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#define RT2661_PCI_USEC_CSR 0x001c
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#define RT2661_H2M_MAILBOX_CSR 0x2100
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#define RT2661_M2H_CMD_DONE_CSR 0x2104
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#define RT2661_HW_BEACON_BASE0 0x2c00
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#define RT2661_MAC_CSR0 0x3000
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#define RT2661_MAC_CSR1 0x3004
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#define RT2661_MAC_CSR2 0x3008
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#define RT2661_MAC_CSR3 0x300c
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#define RT2661_MAC_CSR4 0x3010
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#define RT2661_MAC_CSR5 0x3014
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#define RT2661_MAC_CSR6 0x3018
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#define RT2661_MAC_CSR7 0x301c
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#define RT2661_MAC_CSR8 0x3020
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#define RT2661_MAC_CSR9 0x3024
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#define RT2661_MAC_CSR10 0x3028
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#define RT2661_MAC_CSR11 0x302c
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#define RT2661_MAC_CSR12 0x3030
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#define RT2661_MAC_CSR13 0x3034
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#define RT2661_MAC_CSR14 0x3038
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#define RT2661_MAC_CSR15 0x303c
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#define RT2661_TXRX_CSR0 0x3040
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#define RT2661_TXRX_CSR1 0x3044
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#define RT2661_TXRX_CSR2 0x3048
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#define RT2661_TXRX_CSR3 0x304c
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#define RT2661_TXRX_CSR4 0x3050
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#define RT2661_TXRX_CSR5 0x3054
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#define RT2661_TXRX_CSR6 0x3058
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#define RT2661_TXRX_CSR7 0x305c
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#define RT2661_TXRX_CSR8 0x3060
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#define RT2661_TXRX_CSR9 0x3064
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#define RT2661_TXRX_CSR10 0x3068
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#define RT2661_TXRX_CSR11 0x306c
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#define RT2661_TXRX_CSR12 0x3070
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#define RT2661_TXRX_CSR13 0x3074
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#define RT2661_TXRX_CSR14 0x3078
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#define RT2661_TXRX_CSR15 0x307c
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#define RT2661_PHY_CSR0 0x3080
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#define RT2661_PHY_CSR1 0x3084
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#define RT2661_PHY_CSR2 0x3088
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#define RT2661_PHY_CSR3 0x308c
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#define RT2661_PHY_CSR4 0x3090
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#define RT2661_PHY_CSR5 0x3094
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#define RT2661_PHY_CSR6 0x3098
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#define RT2661_PHY_CSR7 0x309c
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#define RT2661_SEC_CSR0 0x30a0
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#define RT2661_SEC_CSR1 0x30a4
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#define RT2661_SEC_CSR2 0x30a8
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#define RT2661_SEC_CSR3 0x30ac
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#define RT2661_SEC_CSR4 0x30b0
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#define RT2661_SEC_CSR5 0x30b4
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#define RT2661_STA_CSR0 0x30c0
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#define RT2661_STA_CSR1 0x30c4
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#define RT2661_STA_CSR2 0x30c8
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#define RT2661_STA_CSR3 0x30cc
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#define RT2661_STA_CSR4 0x30d0
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#define RT2661_AC0_BASE_CSR 0x3400
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#define RT2661_AC1_BASE_CSR 0x3404
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#define RT2661_AC2_BASE_CSR 0x3408
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#define RT2661_AC3_BASE_CSR 0x340c
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#define RT2661_MGT_BASE_CSR 0x3410
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#define RT2661_TX_RING_CSR0 0x3418
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#define RT2661_TX_RING_CSR1 0x341c
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#define RT2661_AIFSN_CSR 0x3420
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#define RT2661_CWMIN_CSR 0x3424
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#define RT2661_CWMAX_CSR 0x3428
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#define RT2661_TX_DMA_DST_CSR 0x342c
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#define RT2661_TX_CNTL_CSR 0x3430
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#define RT2661_LOAD_TX_RING_CSR 0x3434
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#define RT2661_RX_BASE_CSR 0x3450
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#define RT2661_RX_RING_CSR 0x3454
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#define RT2661_RX_CNTL_CSR 0x3458
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#define RT2661_PCI_CFG_CSR 0x3460
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#define RT2661_INT_SOURCE_CSR 0x3468
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#define RT2661_INT_MASK_CSR 0x346c
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#define RT2661_E2PROM_CSR 0x3470
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#define RT2661_AC_TXOP_CSR0 0x3474
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#define RT2661_AC_TXOP_CSR1 0x3478
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#define RT2661_TEST_MODE_CSR 0x3484
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#define RT2661_IO_CNTL_CSR 0x3498
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#define RT2661_MCU_CODE_BASE 0x4000
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/* possible flags for register HOST_CMD_CSR */
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#define RT2661_KICK_CMD (1 << 7)
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/* Host to MCU (8051) command identifiers */
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#define RT2661_MCU_CMD_SLEEP 0x30
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#define RT2661_MCU_CMD_WAKEUP 0x31
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#define RT2661_MCU_SET_LED 0x50
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#define RT2661_MCU_SET_RSSI_LED 0x52
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/* possible flags for register MCU_CNTL_CSR */
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#define RT2661_MCU_SEL (1 << 0)
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#define RT2661_MCU_RESET (1 << 1)
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#define RT2661_MCU_READY (1 << 2)
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/* possible flags for register MCU_INT_SOURCE_CSR */
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#define RT2661_MCU_CMD_DONE 0xff
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#define RT2661_MCU_WAKEUP (1 << 8)
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#define RT2661_MCU_BEACON_EXPIRE (1 << 9)
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/* possible flags for register H2M_MAILBOX_CSR */
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#define RT2661_H2M_BUSY (1 << 24)
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#define RT2661_TOKEN_NO_INTR 0xff
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/* possible flags for register MAC_CSR5 */
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#define RT2661_ONE_BSSID 3
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/* possible flags for register TXRX_CSR0 */
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/* Tx filter flags are in the low 16 bits */
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#define RT2661_AUTO_TX_SEQ (1 << 15)
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/* Rx filter flags are in the high 16 bits */
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#define RT2661_DISABLE_RX (1 << 16)
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#define RT2661_DROP_CRC_ERROR (1 << 17)
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#define RT2661_DROP_PHY_ERROR (1 << 18)
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#define RT2661_DROP_CTL (1 << 19)
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#define RT2661_DROP_NOT_TO_ME (1 << 20)
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#define RT2661_DROP_TODS (1 << 21)
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#define RT2661_DROP_VER_ERROR (1 << 22)
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#define RT2661_DROP_MULTICAST (1 << 23)
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#define RT2661_DROP_BROADCAST (1 << 24)
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#define RT2661_DROP_ACKCTS (1 << 25)
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/* possible flags for register TXRX_CSR4 */
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#define RT2661_SHORT_PREAMBLE (1 << 19)
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#define RT2661_MRR_ENABLED (1 << 20)
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#define RT2661_MRR_CCK_FALLBACK (1 << 23)
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/* possible flags for register TXRX_CSR9 */
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#define RT2661_TSF_TICKING (1 << 16)
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#define RT2661_TSF_MODE(x) (((x) & 0x3) << 17)
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/* TBTT stands for Target Beacon Transmission Time */
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#define RT2661_ENABLE_TBTT (1 << 19)
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#define RT2661_GENERATE_BEACON (1 << 20)
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/* possible flags for register PHY_CSR0 */
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#define RT2661_PA_PE_2GHZ (1 << 16)
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#define RT2661_PA_PE_5GHZ (1 << 17)
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/* possible flags for register PHY_CSR3 */
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#define RT2661_BBP_READ (1 << 15)
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#define RT2661_BBP_BUSY (1 << 16)
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/* possible flags for register PHY_CSR4 */
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#define RT2661_RF_21BIT (21 << 24)
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#define RT2661_RF_BUSY (1 << 31)
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/* possible values for register STA_CSR4 */
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#define RT2661_TX_STAT_VALID (1 << 0)
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#define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7)
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#define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf)
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#define RT2661_TX_QID(v) (((v) >> 8) & 0xf)
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#define RT2661_TX_SUCCESS 0
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#define RT2661_TX_RETRY_FAIL 6
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/* possible flags for register TX_CNTL_CSR */
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#define RT2661_KICK_MGT (1 << 4)
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/* possible flags for register INT_SOURCE_CSR */
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#define RT2661_TX_DONE (1 << 0)
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#define RT2661_RX_DONE (1 << 1)
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#define RT2661_TX0_DMA_DONE (1 << 16)
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#define RT2661_TX1_DMA_DONE (1 << 17)
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#define RT2661_TX2_DMA_DONE (1 << 18)
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#define RT2661_TX3_DMA_DONE (1 << 19)
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#define RT2661_MGT_DONE (1 << 20)
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/* possible flags for register E2PROM_CSR */
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#define RT2661_C (1 << 1)
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#define RT2661_S (1 << 2)
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#define RT2661_D (1 << 3)
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#define RT2661_Q (1 << 4)
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#define RT2661_93C46 (1 << 5)
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/* Tx descriptor */
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struct rt2661_tx_desc {
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uint32_t flags;
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#define RT2661_TX_BUSY (1 << 0)
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#define RT2661_TX_VALID (1 << 1)
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#define RT2661_TX_MORE_FRAG (1 << 2)
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#define RT2661_TX_NEED_ACK (1 << 3)
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#define RT2661_TX_TIMESTAMP (1 << 4)
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#define RT2661_TX_OFDM (1 << 5)
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#define RT2661_TX_IFS (1 << 6)
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#define RT2661_TX_LONG_RETRY (1 << 7)
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#define RT2661_TX_BURST (1 << 28)
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uint16_t wme;
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#define RT2661_QID(v) (v)
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#define RT2661_AIFSN(v) ((v) << 4)
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#define RT2661_LOGCWMIN(v) ((v) << 8)
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#define RT2661_LOGCWMAX(v) ((v) << 12)
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uint16_t xflags;
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#define RT2661_TX_HWSEQ (1 << 12)
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uint8_t plcp_signal;
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uint8_t plcp_service;
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#define RT2661_PLCP_LENGEXT 0x80
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uint8_t plcp_length_lo;
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uint8_t plcp_length_hi;
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uint32_t iv;
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uint32_t eiv;
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uint8_t offset;
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uint8_t qid;
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#define RT2661_QID_MGT 13
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uint8_t txpower;
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#define RT2661_DEFAULT_TXPOWER 0
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uint8_t reserved1;
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uint32_t addr[RT2661_MAX_SCATTER];
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uint16_t len[RT2661_MAX_SCATTER];
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uint16_t reserved2;
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} __packed;
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/* Rx descriptor */
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struct rt2661_rx_desc {
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uint32_t flags;
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#define RT2661_RX_BUSY (1 << 0)
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#define RT2661_RX_DROP (1 << 1)
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#define RT2661_RX_CRC_ERROR (1 << 6)
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#define RT2661_RX_OFDM (1 << 7)
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#define RT2661_RX_PHY_ERROR (1 << 8)
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#define RT2661_RX_CIPHER_MASK 0x00000600
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uint8_t rate;
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uint8_t rssi;
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uint8_t reserved1;
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uint8_t offset;
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uint32_t iv;
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uint32_t eiv;
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uint32_t reserved2;
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uint32_t physaddr;
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uint32_t reserved3[10];
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} __packed;
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#define RAL_RF1 0
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#define RAL_RF2 2
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#define RAL_RF3 1
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#define RAL_RF4 3
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/* dual-band RF */
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#define RT2661_RF_5225 1
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#define RT2661_RF_5325 2
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/* single-band RF */
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#define RT2661_RF_2527 3
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#define RT2661_RF_2529 4
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#define RT2661_RX_DESC_BACK 4
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#define RT2661_SMART_MODE (1 << 0)
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#define RT2661_BBPR94_DEFAULT 6
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#define RT2661_SHIFT_D 3
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#define RT2661_SHIFT_Q 4
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#define RT2661_EEPROM_MAC01 0x02
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#define RT2661_EEPROM_MAC23 0x03
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#define RT2661_EEPROM_MAC45 0x04
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#define RT2661_EEPROM_ANTENNA 0x10
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#define RT2661_EEPROM_CONFIG2 0x11
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#define RT2661_EEPROM_BBP_BASE 0x13
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#define RT2661_EEPROM_TXPOWER 0x23
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#define RT2661_EEPROM_FREQ_OFFSET 0x2f
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#define RT2661_EEPROM_RSSI_2GHZ_OFFSET 0x4d
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#define RT2661_EEPROM_RSSI_5GHZ_OFFSET 0x4e
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#define RT2661_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
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/*
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* control and status registers access macros
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*/
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#define RAL_READ(sc, reg) \
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bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
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#define RAL_READ_REGION_4(sc, offset, datap, count) \
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bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \
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(datap), (count))
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#define RAL_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define RAL_WRITE_REGION_1(sc, offset, datap, count) \
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bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \
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(datap), (count))
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/*
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* EEPROM access macro
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*/
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#define RT2661_EEPROM_CTL(sc, val) do { \
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RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \
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DELAY(RT2661_EEPROM_DELAY); \
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} while (/* CONSTCOND */0)
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