596 lines
24 KiB
C
596 lines
24 KiB
C
/* $NetBSD: isacsx.h,v 1.3 2005/12/11 12:21:27 christos Exp $ */
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/*
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* Copyright (c) 2001 Gary Jennejohn. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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* 4. Altered versions must be plainly marked as such, and must not be
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* misrepresented as being the original software and/or documentation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h,v 1.1.2.1 2002/04/25 20:26:50 gj Exp $
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*
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* last edit-date: [Wed Jan 24 09:10:42 2001]
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*
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*---------------------------------------------------------------------------*/
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#ifndef I4B_ISACSX_H_
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#define I4B_ISACSX_H_
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/*
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* XXX: Leo: It is unclear to me if this is a necessity for the isacsx too...
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*
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* The ISAC databook specifies a delay of 2.5 DCL clock cycles between
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* writes to the ISAC command register CMDR. This is the delay used to
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* satisfy this requirement.
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*/
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#define I4B_ISAC_CMDRWRDELAY 30
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#if (I4B_ISAC_CMDRWRDELAY > 0)
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#define ISACCMDRWRDELAY() DELAY(I4B_ISAC_CMDRWRDELAY)
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#else
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#warning "I4B_ISAC_CMDRWRDELAY set to 0!"
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#define ISACCMDRWRDELAY()
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#endif
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#define ISACSX_FIFO_LEN 32 /* 32 bytes FIFO on chip */
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#define ISACSX_V13 0x01
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/*
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* definitions of registers and bits for the ISAC-SX ISDN chip.
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*/
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typedef struct isacsx_reg {
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/* 32 byte deep FIFO always first */
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unsigned char isacsx_fifo [ISACSX_FIFO_LEN];
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/* most registers can be read/written, but have different names */
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/* so define a union with read/write names to make that clear */
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union {
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struct {
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unsigned char isacsx_istad;
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unsigned char isacsx_stard;
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unsigned char isacsx_moded;
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unsigned char isacsx_exmd1;
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unsigned char isacsx_timr1;
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unsigned char dummy_25;
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unsigned char isacsx_rbcld;
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unsigned char isacsx_rbchd;
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unsigned char isacsx_rstad;
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unsigned char isacsx_tmd;
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unsigned char dummy_2a;
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unsigned char dummy_2b;
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unsigned char dummy_2c;
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unsigned char dummy_2d;
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unsigned char isacsx_cir0;
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unsigned char isacsx_codr1;
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unsigned char isacsx_tr_conf0;
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unsigned char isacsx_tr_conf1;
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unsigned char isacsx_tr_conf2;
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unsigned char isacsx_tr_sta;
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unsigned char dummy_34;
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unsigned char isacsx_sqrr1;
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unsigned char isacsx_sqrr2;
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unsigned char isacsx_sqrr3;
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unsigned char isacsx_istatr;
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unsigned char isacsx_masktr;
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unsigned char dummy_3a;
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unsigned char dummy_3b;
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unsigned char isacsx_acgf2;
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unsigned char dummy_3d;
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unsigned char dummy_3e;
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unsigned char dummy_3f;
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unsigned char isacsx_cda10;
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unsigned char isacsx_cda11;
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unsigned char isacsx_cda20;
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unsigned char isacsx_cda21;
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unsigned char isacsx_cda_tsdp10;
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unsigned char isacsx_cda_tsdp11;
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unsigned char isacsx_cda_tsdp20;
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unsigned char isacsx_cda_tsdp21;
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unsigned char dummy_48;
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unsigned char dummy_49;
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unsigned char dummy_4a;
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unsigned char dummy_4b;
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unsigned char isacsx_tr_tsdp_bc1;
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unsigned char isacsx_tr_tsdp_bc2;
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unsigned char isacsx_cda1_cr;
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unsigned char isacsx_cda2_cr;
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unsigned char isacsx_tr_cr;
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unsigned char dummy_51;
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unsigned char dummy_52;
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unsigned char isacsx_dci_cr;
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unsigned char isacsx_mon_cr;
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unsigned char isacsx_sds_cr;
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unsigned char dummy_56;
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unsigned char isacsx_iom_cr;
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unsigned char isacsx_sti;
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unsigned char isacsx_msti;
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unsigned char isacsx_sds_conf;
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unsigned char isacsx_mcda;
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unsigned char isacsx_mor;
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unsigned char isacsx_mosr;
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unsigned char isacsx_mocr;
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unsigned char isacsx_msta;
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unsigned char isacsx_ista;
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unsigned char isacsx_auxi;
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unsigned char isacsx_mode1;
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unsigned char isacsx_mode2;
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unsigned char isacsx_id;
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unsigned char isacsx_timr2;
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unsigned char dummy_66;
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unsigned char dummy_67;
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unsigned char dummy_68;
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unsigned char dummy_69;
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unsigned char dummy_6a;
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unsigned char dummy_6b;
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unsigned char dummy_6c;
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unsigned char dummy_6d;
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unsigned char dummy_6e;
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unsigned char dummy_6f;
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} isacsx_r;
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struct {
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unsigned char isacsx_maskd;
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unsigned char isacsx_cmdrd;
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unsigned char isacsx_moded;
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unsigned char isacsx_exmd1;
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unsigned char isacsx_timr1;
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unsigned char isacsx_sap1;
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unsigned char isacsx_sap2;
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unsigned char isacsx_tei1;
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unsigned char isacsx_tei2;
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unsigned char isacsx_tmd;
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unsigned char dummy_2a;
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unsigned char dummy_2b;
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unsigned char dummy_2c;
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unsigned char dummy_2d;
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unsigned char isacsx_cix0;
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unsigned char isacsx_codx1;
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unsigned char isacsx_tr_conf0;
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unsigned char isacsx_tr_conf1;
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unsigned char isacsx_tr_conf2;
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unsigned char dummy_33;
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unsigned char dummy_34;
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unsigned char isacsx_sqrx1;
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unsigned char dummy_36;
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unsigned char dummy_37;
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unsigned char dummy_38;
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unsigned char isacsx_masktr;
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unsigned char dummy_3a;
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unsigned char dummy_3b;
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unsigned char isacsx_acgf2;
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unsigned char dummy_3d;
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unsigned char dummy_3e;
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unsigned char dummy_3f;
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unsigned char isacsx_cda10;
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unsigned char isacsx_cda11;
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unsigned char isacsx_cda20;
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unsigned char isacsx_cda21;
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unsigned char isacsx_cda_tsdp10;
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unsigned char isacsx_cda_tsdp11;
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unsigned char isacsx_cda_tsdp20;
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unsigned char isacsx_cda_tsdp21;
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unsigned char dummy_48;
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unsigned char dummy_49;
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unsigned char dummy_4a;
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unsigned char dummy_4b;
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unsigned char isacsx_tr_tsdp_bc1;
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unsigned char isacsx_tr_tsdp_bc2;
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unsigned char isacsx_cda1_cr;
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unsigned char isacsx_cda2_cr;
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unsigned char isacsx_tr_cr;
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unsigned char dummy_51;
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unsigned char dummy_52;
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unsigned char isacsx_dci_cr;
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unsigned char isacsx_mon_cr;
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unsigned char isacsx_sds_cr;
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unsigned char dummy_56;
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unsigned char isacsx_iom_cr;
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unsigned char isacsx_asti;
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unsigned char isacsx_msti;
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unsigned char isacsx_sds_conf;
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unsigned char dummy_5b;
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unsigned char isacsx_mox;
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unsigned char dummy_5d;
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unsigned char isacsx_mocr;
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unsigned char isacsx_mconf;
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unsigned char isacsx_mask;
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unsigned char isacsx_auxm;
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unsigned char isacsx_mode1;
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unsigned char isacsx_mode2;
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unsigned char isacsx_sres;
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unsigned char isacsx_timr2;
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unsigned char dummy_66;
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unsigned char dummy_67;
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unsigned char dummy_68;
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unsigned char dummy_69;
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unsigned char dummy_6a;
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unsigned char dummy_6b;
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unsigned char dummy_6c;
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unsigned char dummy_6d;
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unsigned char dummy_6e;
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unsigned char dummy_6f;
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} isacsx_w;
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} isacsx_rw;
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} __attribute__ ((packed)) isacsx_reg_t;
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#define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
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/* ISACSX read registers */
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#define i_istad isacsx_rw.isacsx_r.isacsx_istad
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#define I_ISTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istad)
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#define i_stard isacsx_rw.isacsx_r.isacsx_stard
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#define I_STARD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_stard)
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#define i_rmoded isacsx_rw.isacsx_r.isacsx_moded
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#define I_RMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_moded)
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#define i_rexmd1 isacsx_rw.isacsx_r.isacsx_exmd1
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#define I_REXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_exmd1)
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#define i_rtimr1 isacsx_rw.isacsx_r.isacsx_timr1
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#define I_RTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr1)
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#define i_rbcld isacsx_rw.isacsx_r.isacsx_rbcld
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#define I_RBCLD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbcld)
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#define i_rbchd isacsx_rw.isacsx_r.isacsx_rbchd
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#define I_RBCHD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbchd)
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#define i_rstad isacsx_rw.isacsx_r.isacsx_rstad
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#define I_RSTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rstad)
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#define i_rtmd isacsx_rw.isacsx_r.isacsx_tmd
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#define I_RTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tmd)
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#define i_cir0 isacsx_rw.isacsx_r.isacsx_cir0
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#define I_CIR0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cir0)
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#define i_codr1 isacsx_rw.isacsx_r.isacsx_codr1
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#define I_CODR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_codr1)
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#define i_rtr_conf0 isacsx_rw.isacsx_r.isacsx_tr_conf0
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#define I_RTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf0)
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#define i_rtr_conf1 isacsx_rw.isacsx_r.isacsx_tr_conf1
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#define I_RTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf1)
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#define i_rtr_conf2 isacsx_rw.isacsx_r.isacsx_tr_conf2
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#define I_RTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf2)
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#define i_sta isacsx_rw.isacsx_r.isacsx_sta
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#define I_STA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sta)
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#define i_sqrr1 isacsx_rw.isacsx_r.isacsx_sqrr1
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#define I_SQRR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr1)
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#define i_sqrr2 isacsx_rw.isacsx_r.isacsx_sqrr2
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#define I_SQRR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr2)
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#define i_sqrr3 isacsx_rw.isacsx_r.isacsx_sqrr3
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#define I_SQRR3 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr3)
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#define i_istatr isacsx_rw.isacsx_r.isacsx_istatr
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#define I_ISTATR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istatr)
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#define i_rmasktr isacsx_rw.isacsx_r.isacsx_masktr
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#define I_RMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_masktr)
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#define i_racgf2 isacsx_rw.isacsx_r.isacsx_acgf2
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#define I_RACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_acgf2)
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#define i_rcda10 isacsx_rw.isacsx_r.isacsx_cda10
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#define I_RCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda10)
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#define i_rcda11 isacsx_rw.isacsx_r.isacsx_cda11
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#define I_RCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
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#define i_rcda20 isacsx_rw.isacsx_r.isacsx_cda20
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#define I_RCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
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#define i_rcda21 isacsx_rw.isacsx_r.isacsx_cda21
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#define I_RCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
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#define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
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#define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
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#define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
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#define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
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#define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
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#define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
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#define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
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#define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
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#define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
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#define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
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#define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
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#define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
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#define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
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#define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
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#define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
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#define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
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#define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
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#define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
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#define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
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#define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
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#define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
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#define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
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#define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
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#define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
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#define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
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#define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
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#define i_sti isacsx_rw.isacsx_r.isacsx_sti
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#define I_STI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sti)
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#define i_msti isacsx_rw.isacsx_r.isacsx_msti
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#define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
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#define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
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#define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
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#define i_mcda isacsx_rw.isacsx_r.isacsx_mcda
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#define I_MCDA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mcda)
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#define i_mor isacsx_rw.isacsx_r.isacsx_mor
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#define I_MOR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mor)
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#define i_mosr isacsx_rw.isacsx_r.isacsx_mosr
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#define I_MOSR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mosr)
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#define i_rmocr isacsx_rw.isacsx_r.isacsx_mocr
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#define I_RMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mocr)
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#define i_msta isacsx_rw.isacsx_r.isacsx_msta
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#define I_MSTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msta)
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#define i_ista isacsx_rw.isacsx_r.isacsx_ista
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#define I_ISTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_ista)
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#define i_auxi isacsx_rw.isacsx_r.isacsx_auxi
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#define I_AUXI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_auxi)
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#define i_rmode1 isacsx_rw.isacsx_r.isacsx_mode1
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#define I_RMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode1)
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#define i_rmode2 isacsx_rw.isacsx_r.isacsx_mode2
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#define I_RMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode2)
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#define i_id isacsx_rw.isacsx_r.isacsx_id
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#define I_ID REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_id)
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#define i_rtimr2 isacsx_rw.isacsx_r.isacsx_timr2
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#define I_RTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr2)
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/* ISAC write registers - isacsx_mode, isacsx_timr, isacsx_star2, isacsx_spcr, */
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/* isacsx_c1r, isacsx_c2r, isacsx_adf2 see read registers */
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#define i_maskd isacsx_rw.isacsx_w.isacsx_maskd
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#define I_MASKD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_maskd)
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#define i_cmdrd isacsx_rw.isacsx_w.isacsx_cmdrd
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#define I_CMDRD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cmdrd)
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#define i_wmoded isacsx_rw.isacsx_w.isacsx_moded
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#define I_WMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_moded)
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#define i_wexmd1 isacsx_rw.isacsx_w.isacsx_exmd1
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#define I_WEXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_exmd1)
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#define i_wtimr1 isacsx_rw.isacsx_w.isacsx_timr1
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#define I_WTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr1)
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#define i_sap1 isacsx_rw.isacsx_w.isacsx_sap1
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#define I_SAP1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap1)
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#define i_sap2 isacsx_rw.isacsx_w.isacsx_sap2
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#define I_SAP2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap2)
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#define i_tei1 isacsx_rw.isacsx_w.isacsx_tei1
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#define i_tei2 isacsx_rw.isacsx_w.isacsx_tei2
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#define i_wtmd isacsx_rw.isacsx_w.isacsx_tmd
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#define I_WTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tmd)
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#define i_cix0 isacsx_rw.isacsx_w.isacsx_cix0
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#define I_CIX0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cix0)
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#define i_codx1 isacsx_rw.isacsx_w.isacsx_codx1
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#define I_CODX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_codx1)
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#define i_wtr_conf0 isacsx_rw.isacsx_w.isacsx_tr_conf0
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#define I_WTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf0)
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#define i_wtr_conf1 isacsx_rw.isacsx_w.isacsx_tr_conf1
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#define I_WTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf1)
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#define i_wtr_conf2 isacsx_rw.isacsx_w.isacsx_tr_conf2
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#define I_WTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf2)
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#define i_sqrx1 isacsx_rw.isacsx_w.isacsx_sqrx1
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#define I_SQRX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sqrx1)
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#define i_wmasktr isacsx_rw.isacsx_w.isacsx_masktr
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#define I_WMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_masktr)
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#define i_wacgf2 isacsx_rw.isacsx_w.isacsx_acgf2
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#define I_WACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_acgf2)
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#define i_wcda10 isacsx_rw.isacsx_w.isacsx_cda10
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#define I_WCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cda10)
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#define i_wcda11 isacsx_rw.isacsx_r.isacsx_cda11
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#define I_WCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
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#define i_wcda20 isacsx_rw.isacsx_r.isacsx_cda20
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#define I_WCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
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#define i_wcda21 isacsx_rw.isacsx_r.isacsx_cda21
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#define I_WCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
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#define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
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#define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
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#define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
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#define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
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#define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
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#define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
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#define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
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#define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
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#define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
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#define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
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#define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
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#define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
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#define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
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#define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
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#define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
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#define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
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#define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
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#define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
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#define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
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#define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
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#define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
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#define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
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#define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
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#define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
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#define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
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#define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
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#define i_asti isacsx_rw.isacsx_r.isacsx_asti
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#define I_ASTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_asti)
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#define i_msti isacsx_rw.isacsx_r.isacsx_msti
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#define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
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#define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
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#define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
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#define i_mox isacsx_rw.isacsx_w.isacsx_mox
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#define I_MOX REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mox)
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#define i_wmocr isacsx_rw.isacsx_w.isacsx_mocr
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#define I_WMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mocr)
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#define i_mconf isacsx_rw.isacsx_w.isacsx_mconf
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#define I_MCONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mconf)
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#define i_mask isacsx_rw.isacsx_w.isacsx_mask
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#define I_MASK REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mask)
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#define i_auxm isacsx_rw.isacsx_w.isacsx_auxm
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#define I_AUXM REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_auxm)
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#define i_wmode1 isacsx_rw.isacsx_w.isacsx_mode1
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#define I_WMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode1)
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#define i_wmode2 isacsx_rw.isacsx_w.isacsx_mode2
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#define I_WMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode2)
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#define i_sres isacsx_rw.isacsx_w.isacsx_sres
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#define I_SRES REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sres)
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#define i_wtimr2 isacsx_rw.isacsx_w.isacsx_timr2
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#define I_WTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr2)
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#define ISACSX_ISTAD_RME 0x80
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#define ISACSX_ISTAD_RPF 0x40
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#define ISACSX_ISTAD_RFO 0x20
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#define ISACSX_ISTAD_XPR 0x10
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#define ISACSX_ISTAD_XMR 0x08
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#define ISACSX_ISTAD_XDU 0x04
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#define ISACSX_MASKD_RME 0x80
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#define ISACSX_MASKD_RPF 0x40
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#define ISACSX_MASKD_RFO 0x20
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#define ISACSX_MASKD_XPR 0x10
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#define ISACSX_MASKD_XMR 0x08
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#define ISACSX_MASKD_XDU 0x04
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/* these must always be set */
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#define ISACSX_MASKD_LOW 0x03
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#define ISACSX_MASKD_ALL 0xff
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#define ISACSX_STARD_XDOV 0x80
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#define ISACSX_STARD_XFW 0x40
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#define ISACSX_STARD_RAC1 0x08
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#define ISACSX_STARD_XAC1 0x02
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#define ISACSX_CMDRD_RMC 0x80
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#define ISACSX_CMDRD_RRES 0x40
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#define ISACSX_CMDRD_STI 0x10
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#define ISACSX_CMDRD_XTF 0x08
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#define ISACSX_CMDRD_XME 0x02
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#define ISACSX_CMDRD_XRES 0x01
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#define ISACSX_MODED_MDS2 0x80
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#define ISACSX_MODED_MDS1 0x40
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#define ISACSX_MODED_MDS0 0x20
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#define ISACSX_MODED_RAC 0x08
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#define ISACSX_MODED_DIM2 0x04
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#define ISACSX_MODED_DIM1 0x02
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#define ISACSX_MODED_DIM0 0x01
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/* default */
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#define ISACSX_EXMD1_XFBS_32 0x00 /* XFIFO is 32 bytes */
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#define ISACSX_EXMD1_XFBS_16 0x80 /* XFIFO is 16 bytes */
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/* default */
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#define ISACSX_EXMD1_RFBS_32 0x00 /* XFIFO is 32 bytes */
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#define ISACSX_EXMD1_RFBS_16 0x20 /* XFIFO is 16 bytes */
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#define ISACSX_EXMD1_RFBS_08 0x40 /* XFIFO is 8 bytes */
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#define ISACSX_EXMD1_RFBS_04 0x60 /* XFIFO is 4 bytes */
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#define ISACSX_EXMD1_SRA 0x10
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#define ISACSX_EXMD1_XCRC 0x08
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#define ISACSX_EXMD1_RCRC 0x04
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#define ISACSX_EXMD1_ITF 0x01
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#define ISACSX_RSTAD_VFR 0x80
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#define ISACSX_RSTAD_RDO 0x40
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#define ISACSX_RSTAD_CRC 0x20
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#define ISACSX_RSTAD_RAB 0x10
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#define ISACSX_RSTAD_SA1 0x08
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#define ISACSX_RSTAD_SA0 0x04
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#define ISACSX_RSTAD_CR 0x02
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#define ISACSX_RSTAD_TA 0x01
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#define ISACSX_RSTAD_MASK 0xf0 /* the interesting bits */
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#define ISACSX_RBCHD_OV 0x10
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/* the other 4 bits are the high bits of the receive byte count */
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#define ISACSX_CIR0_CIC0 0x08
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/* CODR0 >> 4 */
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#define ISACSX_CIR0_IPU 0x07
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#define ISACSX_CIR0_IDR 0x00
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#define ISACSX_CIR0_ISD 0x02
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#define ISACSX_CIR0_IDIS 0x03
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#define ISACSX_CIR0_IEI 0x06
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#define ISACSX_CIR0_IRSY 0x04
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#define ISACSX_CIR0_IARD 0x08
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#define ISACSX_CIR0_ITI 0x0a
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#define ISACSX_CIR0_IATI 0x0b
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#define ISACSX_CIR0_IAI8 0x0c
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#define ISACSX_CIR0_IAI10 0x0d
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#define ISACSX_CIR0_IDID 0x0f
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#define ISACSX_IOM_CR_SPU 0x80
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#define ISACSX_IOM_CR_CI_CS 0x20
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#define ISACSX_IOM_CR_TIC_DIS 0x10
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#define ISACSX_IOM_CR_EN_BCL 0x08
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#define ISACSX_IOM_CR_CLKM 0x04
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#define ISACSX_IOM_CR_DIS_OD 0x02
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#define ISACSX_IOM_CR_DIS_IOM 0x01
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#define ISACSX_CI_MASK 0x0f
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#define ISACSX_CIX0_BAC 0x01
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/* in IOM-2 mode the low bits are always 1 */
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#define ISACSX_CIX0_LOW 0x0e
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/* C/I codes from bits 7-4 (>> 4 & 0xf) */
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/* the commands */
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#define ISACSX_CIX0_CTIM 0
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#define ISACSX_CIX0_CRS 0x01
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/* test mode only */
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#define ISACSX_CIX0_CSSSP 0x02
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/* test mode only */
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#define ISACSX_CIX0_CSSCP 0x03
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#define ISACSX_CIX0_CAR8 0x08
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#define ISACSX_CIX0_CAR10 0x09
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#define ISACSX_CIX0_CARL 0x0a
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#define ISACSX_CIX0_CDIU 0x0f
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/* Interrupt, General Configuration Registers */
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#define ISACSX_ISTA_ST 0x20
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#define ISACSX_ISTA_CIC 0x10
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#define ISACSX_ISTA_AUX 0x08
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#define ISACSX_ISTA_TRAN 0x04
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#define ISACSX_ISTA_MOS 0x02
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#define ISACSX_ISTA_ICD 0x01
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#define ISACSX_MASK_ST 0x20
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#define ISACSX_MASK_CIC 0x10
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#define ISACSX_MASK_AUX 0x08
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#define ISACSX_MASK_TRAN 0x04
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#define ISACSX_MASK_MOS 0x02
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#define ISACSX_MASK_ICD 0x01
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#define ISACSX_AUXI_EAW 0x20
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#define ISACSX_AUXI_WOV 0x10
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#define ISACSX_AUXI_TIN2 0x08
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#define ISACSX_AUXI_TIN1 0x04
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#define ISACSX_AUXM_EAW 0x20
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#define ISACSX_AUXM_WOV 0x10
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#define ISACSX_AUXM_TIN2 0x08
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#define ISACSX_AUXM_TIN1 0x04
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#define ISACSX_MODE1_WTC1 0x10
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#define ISACSX_MODE1_WTC2 0x08
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#define ISACSX_MODE1_CFS 0x04
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#define ISACSX_MODE1_RSS2 0x02
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#define ISACSX_MODE1_RSS1 0x01
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#define ISACSX_MODE2_INT_POL 0x08
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#define ISACSX_MODE2_PPSDX 0x01
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#define ISACSX_ID_MASK 0x2F /* 0x01 = Version 1.3 */
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extern unsigned char isacsx_imaskd;
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extern unsigned char isacsx_imask;
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#endif /* I4B_ISACSX_H_ */
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