236 lines
6.8 KiB
C
236 lines
6.8 KiB
C
/* $NetBSD: if_axenreg.h,v 1.15 2019/07/31 09:13:16 mrg Exp $ */
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/* $OpenBSD: if_axenreg.h,v 1.1 2013/10/07 05:37:41 yuo Exp $ */
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/*
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* Copyright (c) 2013 Yojiro UO <yuo@openbsd.org>. All right reserved.
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*
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*/
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#include <sys/rndsource.h>
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/*
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* Definitions for the ASIX Electronics AX88179 to ethernet controller.
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*/
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#define AXEN_PHY_ID 0x0003
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#define AXEN_MCAST_FILTER_SIZE 8
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/* unit: KB */
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#define AXEN_BUFSZ_LS 8
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#define AXEN_BUFSZ_HS 16
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#define AXEN_BUFSZ_SS 24
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#define AXEN_REV_UA1 0
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#define AXEN_REV_UA2 1
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/* receive header */
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/*
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* +-multicast/broadcast
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* | +-rx_ok
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* | | ++-----L3_type (1:ipv4, 0/2:ipv6)
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* pkt_len(13) | | ||+ ++-L4_type(0: icmp, 1: UDP, 4: TCP)
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* |765|43210 76543210|7654 3210 7654 3210|
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* | +-crc_err |+-L4_err |+-L4_CSUM_ERR
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* +--drop_err +--L3_err +--L3_CSUM_ERR
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*
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* ex) pkt_hdr 0x00680820
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* drop_err, crc_err: none
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* pkt_length = 104 byte
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* 0x0820 = 0000 1000 0010 0000 => ipv4 icmp
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*
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* ex) pkt_hdr 0x004c8800
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* drop_err, crc_err: none
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* pkt_length = 76 byte
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* 0x8800 = 1000 1000 0000 0000 => ipv6 mcast icmp
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*
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* [memo]
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* 0x0820: ipv4 icmp 0000 1000 0010 0000
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* 0x8820: ipv4 icmp (broadcast) 1000 1000 0010 0000
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* 0x0824: ipv4 udp (nping) 0000 1000 0010 0100
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* 0x0830: ipv4 tcp (ssh) 0000 1000 0011 0000
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*
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* 0x0800: ipv6 icmp 0000 1000 0000 0000
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* 0x8800: ipv6 icmp (multicast) 1000 1000 0000 0000
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* 0x8844: ipv6 UDP/MDNS mcast 1000 1000 0100 0100
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* 0x0850: ipv6 tcp (ssh) 0000 1000 0101 0000
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*/
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#define AXEN_RXHDR_DROP_ERR (1 << 31)
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#define AXEN_RXHDR_CRC_ERR (1 << 29)
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#define AXEN_RXHDR_MCAST (1 << 15)
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#define AXEN_RXHDR_RX_OK (1 << 11)
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#define AXEN_RXHDR_L3_ERR (1 << 9)
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#define AXEN_RXHDR_L4_ERR (1 << 8)
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#define AXEN_RXHDR_L3CSUM_ERR (1 << 1)
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#define AXEN_RXHDR_L4CSUM_ERR (1 << 0)
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/* L4 packet type (3bit) */
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#define AXEN_RXHDR_L4_TYPE_MASK 0x0000001c
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#define AXEN_RXHDR_L4_TYPE_OFFSET 2
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#define AXEN_RXHDR_L4_TYPE_ICMP 0x0
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#define AXEN_RXHDR_L4_TYPE_UDP 0x1
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#define AXEN_RXHDR_L4_TYPE_TCP 0x4
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/* L3 packet type (2bit) */
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#define AXEN_RXHDR_L3_TYPE_MASK 0x00000060
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#define AXEN_RXHDR_L3_TYPE_OFFSET 5
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#define AXEN_RXHDR_L3_TYPE_UNDEF 0x0
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#define AXEN_RXHDR_L3_TYPE_IPV4 0x1
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#define AXEN_RXHDR_L3_TYPE_IPV6 0x2
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/*
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* commands
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*/
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#define AXEN_CMD_LEN(x) (((x) & 0xF000) >> 12)
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#define AXEN_CMD_DIR(x) (((x) & 0x0F00) >> 8)
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#define AXEN_CMD_CMD(x) ((x) & 0x00FF)
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/* ---MAC--- */
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/* 1byte cmd */
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#define AXEN_CMD_MAC_READ 0x1001
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#define AXEN_CMD_MAC_WRITE 0x1101
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#define AXEN_USB_UPLINK 0x02
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#define AXEN_USB_FS 0x01
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#define AXEN_USB_HS 0x02
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#define AXEN_USB_SS 0x04
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#define AXEN_GENERAL_STATUS 0x03
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#define AXEN_GENERAL_STATUS_MASK 0x4
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#define AXEN_REV0 0x0
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#define AXEN_REV1 0x4
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#define AXEN_UNK_05 0x05
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#define AXEN_MAC_EEPROM_ADDR 0x07
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#define AXEN_MAC_EEPROM_READ 0x08
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#define AXEN_MAC_EEPROM_CMD 0x0a
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#define AXEN_EEPROM_READ 0x04
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#define AXEN_EEPROM_WRITE 0x08
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#define AXEN_EEPROM_BUSY 0x10
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#define AXEN_MONITOR_MODE 0x24
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#define AXEN_MONITOR_NONE 0x00
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#define AXEN_MONITOR_RWLC 0x02
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#define AXEN_MONITOR_RWMP 0x04
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#define AXEN_MONITOR_RWWF 0x08
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#define AXEN_MONITOR_RW_FLAG 0x10
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#define AXEN_MONITOR_PMEPOL 0x20
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#define AXEN_MONITOR_PMETYPE 0x40
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#define AXEN_UNK_28 0x28
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#define AXEN_PHYCLK 0x33
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#define AXEN_PHYCLK_BCS 0x01
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#define AXEN_PHYCLK_ACS 0x02
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#define AXEN_PHYCLK_ULR 0x08
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#define AXEN_PHYCLK_ACSREQ 0x10
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#define AXEN_RX_COE 0x34
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#define AXEN_RXCOE_OFF 0x00
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#define AXEN_RXCOE_IPv4 0x01
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#define AXEN_RXCOE_TCPv4 0x02
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#define AXEN_RXCOE_UDPv4 0x04
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#define AXEN_RXCOE_ICMP 0x08
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#define AXEN_RXCOE_IGMP 0x10
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#define AXEN_RXCOE_TCPv6 0x20
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#define AXEN_RXCOE_UDPv6 0x40
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#define AXEN_RXCOE_ICMPv6 0x80
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#define AXEN_TX_COE 0x35
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#define AXEN_TXCOE_OFF 0x00
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#define AXEN_TXCOE_IPv4 0x01
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#define AXEN_TXCOE_TCPv4 0x02
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#define AXEN_TXCOE_UDPv4 0x04
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#define AXEN_TXCOE_ICMP 0x08
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#define AXEN_TXCOE_IGMP 0x10
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#define AXEN_TXCOE_TCPv6 0x20
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#define AXEN_TXCOE_UDPv6 0x40
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#define AXEN_TXCOE_ICMPv6 0x80
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#define AXEN_PAUSE_HIGH_WATERMARK 0x54
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#define AXEN_PAUSE_LOW_WATERMARK 0x55
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/* 2byte cmd */
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#define AXEN_CMD_MAC_READ2 0x2001
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#define AXEN_CMD_MAC_WRITE2 0x2101
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#define AXEN_MAC_RXCTL 0x0b
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#define AXEN_RXCTL_STOP 0x0000
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#define AXEN_RXCTL_PROMISC 0x0001
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#define AXEN_RXCTL_ACPT_ALL_MCAST 0x0002
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#define AXEN_RXCTL_HA8B 0x0004
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#define AXEN_RXCTL_AUTOB 0x0008
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#define AXEN_RXCTL_ACPT_MCAST 0x0010
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#define AXEN_RXCTL_ACPT_PHY_MCAST 0x0020
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#define AXEN_RXCTL_START 0x0080
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#define AXEN_RXCTL_DROPCRCERR 0x0100
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#define AXEN_RXCTL_IPE 0x0200
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#define AXEN_RXCTL_TXPADCRC 0x0400
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#define AXEN_MEDIUM_STATUS 0x22
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#define AXEN_MEDIUM_NONE 0x0000
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#define AXEN_MEDIUM_GIGA 0x0001
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#define AXEN_MEDIUM_FDX 0x0002
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#define AXEN_MEDIUM_ALWAYS_ONE 0x0004
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#define AXEN_MEDIUM_EN_125MHZ 0x0008
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#define AXEN_MEDIUM_RXFLOW_CTRL_EN 0x0010
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#define AXEN_MEDIUM_TXFLOW_CTRL_EN 0x0020
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#define AXEN_MEDIUM_RECV_EN 0x0100
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#define AXEN_MEDIUM_PS 0x0200
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#define AXEN_MEDIUM_JUMBO_EN 0x8040
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#define AXEN_PHYPWR_RSTCTL 0x26
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#define AXEN_PHYPWR_RSTCTL_BZ 0x0010
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#define AXEN_PHYPWR_RSTCTL_IPRL 0x0020
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#define AXEN_PHYPWR_RSTCTL_AUTODETACH 0x1000
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#define AXEN_CMD_EEPROM_READ 0x2004
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#define AXEN_EEPROM_STAT 0x43
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/* 5byte cmd */
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#define AXEN_CMD_MAC_SET_RXSR 0x5101
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#define AXEN_RX_BULKIN_QCTRL 0x2e
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/* 6byte cmd */
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#define AXEN_CMD_MAC_READ_ETHER 0x6001
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#define AXEN_CMD_MAC_NODE_ID 0x10
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/* 8byte cmd */
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#define AXEN_CMD_MAC_READ_FILTER 0x8001
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#define AXEN_CMD_MAC_WRITE_FILTER 0x8101
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#define AXEN_FILTER_MULTI 0x16
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/* ---PHY--- */
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/* 2byte cmd */
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#define AXEN_CMD_MII_READ_REG 0x2002
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#define AXEN_CMD_MII_WRITE_REG 0x2102
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/* ========= */
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#define AXEN_GPIO0_EN 0x01
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#define AXEN_GPIO0 0x02
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#define AXEN_GPIO1_EN 0x04
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#define AXEN_GPIO1 0x08
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#define AXEN_GPIO2_EN 0x10
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#define AXEN_GPIO2 0x20
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#define AXEN_GPIO_RELOAD_EEPROM 0x80
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#define AXEN_TIMEOUT 1000
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#ifndef AXEN_RX_LIST_CNT
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#define AXEN_RX_LIST_CNT 4 /* 22 for SS mode in Linux driver */
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#endif
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#ifndef AXEN_TX_LIST_CNT
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#define AXEN_TX_LIST_CNT 4 /* 60 */
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#endif
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#define AXEN_CONFIG_NO 1
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#define AXEN_IFACE_IDX 0
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struct axen_qctrl {
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uint8_t ctrl;
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uint8_t timer_low;
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uint8_t timer_high;
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uint8_t bufsize;
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uint8_t ifg;
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} __packed;
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struct axen_sframe_hdr {
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uint32_t plen; /* packet length */
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uint32_t gso;
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} __packed;
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