ad3073beaf
as the Shark's CS8900 Ethernet, which want to use the DMA controller in this mode (as opposed to single mode). [Editor's note: committed from a Shark using a new bus_dma back-end and a CS8900 driver converted to use the MI code :-]
140 lines
5.3 KiB
C
140 lines
5.3 KiB
C
/* $NetBSD: isadmavar.h,v 1.14 1998/06/28 06:59:36 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_ISA_ISADMAVAR_H_
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#define _DEV_ISA_ISADMAVAR_H_
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#define MAX_ISADMA 65536
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#define DMAMODE_WRITE 0x00
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#define DMAMODE_READ 0x01
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#define DMAMODE_LOOP 0x02
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#define DMAMODE_LOOPDEMAND 0x04
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/*
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* ISA DMA state. This structure is provided by the ISA chipset
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* DMA entry points to the generic back-end functions that actually
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* frob the controller.
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*/
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struct isa_dma_state {
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struct device *ids_dev; /* associated device (for dv_xname) */
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bus_space_tag_t ids_bst; /* bus space tag for DMA controller */
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bus_space_handle_t ids_dma1h; /* handle for DMA controller #1 */
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bus_space_handle_t ids_dma2h; /* handle for DMA controller #2 */
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bus_space_handle_t ids_dmapgh; /* handle for DMA page registers */
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bus_dma_tag_t ids_dmat; /* DMA tag for DMA controller */
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bus_dmamap_t ids_dmamaps[8]; /* DMA maps for each channel */
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bus_size_t ids_dmalength[8]; /* size of DMA transfer per channel */
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int ids_drqmap; /* available DRQs (bitmap) */
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int ids_dmareads; /* state for isa_dmadone() (bitmap) */
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int ids_dmafinished; /* DMA completion state (bitmap) */
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int ids_masked; /* masked channels (bitmap) */
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int ids_frozen; /* `frozen' count */
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int ids_initialized; /* only initialize once... */
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};
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#define ISA_DMA_DRQ_ISFREE(state, drq) \
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(((state)->ids_drqmap & (1 << (drq))) == 0)
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#define ISA_DMA_DRQ_ALLOC(state, drq) \
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(state)->ids_drqmap |= (1 << (drq))
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#define ISA_DMA_DRQ_FREE(state, drq) \
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(state)->ids_drqmap &= ~(1 << (drq))
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#define ISA_DMA_MASK_SET(state, drq) \
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(state)->ids_masked |= (1 << (drq))
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#define ISA_DMA_MASK_CLR(state, drq) \
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(state)->ids_masked &= ~(1 << (drq))
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/*
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* Memory list used by _isa_malloc().
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*/
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struct isa_mem {
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struct isa_dma_state *ids;
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int chan;
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bus_size_t size;
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bus_addr_t addr;
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caddr_t kva;
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struct isa_mem *next;
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};
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#ifdef _KERNEL
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struct proc;
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void _isa_dmainit __P((struct isa_dma_state *, bus_space_tag_t,
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bus_dma_tag_t, struct device *));
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int _isa_dmacascade __P((struct isa_dma_state *, int));
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int _isa_dmamap_create __P((struct isa_dma_state *, int,
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bus_size_t, int));
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void _isa_dmamap_destroy __P((struct isa_dma_state *, int));
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int _isa_dmastart __P((struct isa_dma_state *, int, void *, bus_size_t,
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struct proc *, int, int));
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void _isa_dmaabort __P((struct isa_dma_state *, int));
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bus_size_t _isa_dmacount __P((struct isa_dma_state *, int));
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int _isa_dmafinished __P((struct isa_dma_state *, int));
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void _isa_dmadone __P((struct isa_dma_state *, int));
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void _isa_dmafreeze __P((struct isa_dma_state *));
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void _isa_dmathaw __P((struct isa_dma_state *));
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int _isa_dmamem_alloc __P((struct isa_dma_state *, int, bus_size_t,
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bus_addr_t *, int));
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void _isa_dmamem_free __P((struct isa_dma_state *, int, bus_addr_t,
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bus_size_t));
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int _isa_dmamem_map __P((struct isa_dma_state *, int, bus_addr_t,
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bus_size_t, caddr_t *, int));
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void _isa_dmamem_unmap __P((struct isa_dma_state *, int, caddr_t,
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size_t));
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int _isa_dmamem_mmap __P((struct isa_dma_state *, int, bus_addr_t,
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bus_size_t, int, int, int));
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int _isa_drq_isfree __P((struct isa_dma_state *, int));
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void *_isa_malloc __P((struct isa_dma_state *, int, size_t, int, int));
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void _isa_free __P((void *, int));
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int _isa_mappage __P((void *, int, int));
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#endif /* _KERNEL */
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#endif /* _DEV_ISA_ISADMAVAR_H_ */
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