299 lines
12 KiB
C
299 lines
12 KiB
C
/*
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* Copyright (c) 1988, 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)espreg.h 8.1 (Berkeley) 6/11/93
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*
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* from: Header: espreg.h,v 1.7 92/11/26 02:28:10 torek Exp (LBL)
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* $Id: espreg.h,v 1.1 1993/10/02 10:23:52 deraadt Exp $
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*
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* Derived from Mary Baker's devSCSIC90.c from the Berkeley
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* Sprite project, which is:
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*
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* Copyright 1988 Regents of the University of California
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. The University of California
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*/
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/*
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* Emulex ESP100, ESP100A, and ESP200 registers, as found on the
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* Sun-4c Sbus.
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*
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* The registers are all bytes, and all on longword boundaries.
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* Grody to the max!
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*/
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struct espreg {
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u_char esp_tcl; /* transfer count low (byte 0) (rw) */
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u_char esp_xxx0[3];
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u_char esp_tch; /* transfer count high (byte 1) (rw) */
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u_char esp_xxx1[3];
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u_char esp_fifo; /* fifo data register (rw) */
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u_char esp_xxx2[3];
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u_char esp_cmd; /* command (rw) */
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u_char esp_xxx3[3];
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u_char esp_stat; /* status (ro); scsi id (wo) */
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#define esp_id esp_stat
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u_char esp_xxx4[3];
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u_char esp_intr; /* interrupt (ro); timeout (wo) */
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#define esp_timeout esp_intr
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u_char esp_xxx5[3];
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u_char esp_step; /* sequence step (ro); sync period (wo) */
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#define esp_syncperiod esp_step
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u_char esp_xxx6[3];
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u_char esp_fflags; /* fifo flags (ro); sync offset (wo) */
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#define esp_syncoff esp_fflags
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u_char esp_xxx7[3];
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u_char esp_conf1; /* configuration #1 (rw) */
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u_char esp_xxx8[3];
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u_char esp_ccf; /* clock conversion factor (wo) */
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u_char esp_xxx9[3];
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u_char esp_test; /* test (do not use) */
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u_char esp_xxxA[3];
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u_char esp_conf2; /* configuration #2 (rw) */
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u_char esp_xxxB[3];
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u_char esp_conf3; /* configuration #3 (rw, ESP-236) */
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u_char esp_xxxC[3];
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};
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/* THE REST OF THESE NAMES COULD STAND TO BE SHORTENED */
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/*
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* Bits in esp_cmd. Note that the cmd register is two levels deep (see
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* Emulex documentation, p. 4-3); our typical usage is to set the command,
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* then set it again with DMA.
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*
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* Targets will use disconnected and target mode commands; initiators will use
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* disconnected and initiator mode commands. Bit 0x40 indicates disconnected
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* mode, 0x20 target mode, and 0x10 initiator mode. (However, everyone can
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* use the miscellaneous commands, which have none of those bits set.)
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*/
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#define ESPCMD_DMA 0x80 /* flag => do DMA */
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/* miscellaneous */
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#define ESPCMD_NOP 0x00 /* do nothing */
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#define ESPCMD_FLUSH_FIFO 0x01 /* flush FIFO */
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#define ESPCMD_RESET_CHIP 0x02 /* reset ESP chip */
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#define ESPCMD_RESET_BUS 0x03 /* reset SCSI bus */
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/* disconnected */
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#define ESPCMD_RESEL_SEQ 0x40 /* reselect sequence */
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#define ESPCMD_SEL_NATN 0x41 /* select without ATN sequence */
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#define ESPCMD_SEL_ATN 0x42 /* select with ATN sequence */
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#define ESPCMD_SEL_ATNS 0x43 /* select with ATN & stop seq */
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#define ESPCMD_SEL_ENA 0x44 /* enable selection/reselection */
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#define ESPCMD_SEL_DIS 0x45 /* disable selection/reselection */
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#define ESPCMD_SEL_ATN3 0x46 /* select with ATN3 sequence */
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/* target state */
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#define ESPCMD_SEND_MSG 0x20 /* send message */
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#define ESPCMD_SEND_STATUS 0x21 /* send status */
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#define ESPCMD_SEND_DATA 0x22 /* send data */
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#define ESPCMD_DIS_SEQ 0x23 /* disconnect sequence */
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#define ESPCMD_TERM_SEQ 0x24 /* terminate sequence */
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#define ESPCMD_TARG_COMP 0x25 /* target command complete sequence */
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#define ESPCMD_DISCONNECT 0x27 /* disconnect */
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#define ESPCMD_RCV_MSG 0x28 /* receive message sequence */
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#define ESPCMD_RCV_CMD 0x29 /* receive command */
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#define ESPCMD_RCV_DATA 0x2a /* receive data */
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#define ESPCMD_REC_CMD_SEQ 0x2b /* receive command sequence */
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#define ESPCMD_STOP_DMA 0x04 /* stop DMA (see p. 4-6) */
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/* ESPCMD_TARG_ABORT 0x06 target abort sequence */
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/* initiator state */
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#define ESPCMD_XFER_INFO 0x10 /* transfer information */
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#define ESPCMD_INIT_COMP 0x11 /* initiator command complete seq */
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#define ESPCMD_MSG_ACCEPT 0x12 /* message accepted */
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#define ESPCMD_XFER_PAD 0x18 /* transfer pad (use only w/ DMA) */
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#define ESPCMD_SET_ATN 0x1a /* set ATN */
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#define ESPCMD_RESET_ATN 0x1b /* reset ATN */
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/*
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* Bits in esp_stat.
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* Bits 3 through 7 are latched until esp_intr is read;
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* bits 0 through 2 (the phase) are not normally latched.
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* The interrupt bit is set even if interrupts are disabled.
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* Hardware or software reset, or reading esp_intr, will
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* clear the interrupt and turn off ESPSTAT_INT.
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*/
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#ifdef notdef
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#define ESPSTAT_INT 0x80 /* ASC interrupting processor */
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#else
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#define ESPSTAT_XXX 0x80 /* rumored unreliable: use dma IP */
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#endif
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#define ESPSTAT_GE 0x40 /* gross error */
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#define ESPSTAT_PE 0x20 /* parity error */
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#define ESPSTAT_ERR 0x60 /* pseudo composite */
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#define ESPSTAT_TC 0x10 /* terminal count */
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#define ESPSTAT_VGC 0x08 /* valid group code */
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#define ESPSTAT_MSG 0x04 /* MSG line from SCSI bus */
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#define ESPSTAT_CD 0x02 /* CD line from SCSI bus */
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#define ESPSTAT_IO 0x01 /* IO line from SCSI bus */
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#define ESPSTAT_PHASE 7 /* phase mask */
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#define ESPPHASE_DATA_OUT 0 /* data out */
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#define ESPPHASE_DATA_IN 1 /* data in */
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#define ESPPHASE_CMD 2 /* command */
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#define ESPPHASE_STATUS 3 /* status */
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#define ESPPHASE_MSG_OUT 6 /* message out (w.r.t. initiator) */
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#define ESPPHASE_MSG_IN 7 /* message in */
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#ifdef ESP_PHASE_NAMES
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/* printed as `... during %s phase' */
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char *espphases[] =
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{ "data out", "data in", "command", "status",
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"impossible(4)", "impossible(5)", "message out", "message in" };
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#endif
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#define ESPSTAT_BITS "\20\10INT\7GE\6PE\5TC\4VGC\3MSG\2CD\1IO"
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/*
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* Bits in esp_intr.
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*/
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#define ESPINTR_SBR 0x80 /* SCSI bus reset detected */
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#define ESPINTR_ILC 0x40 /* illegal command */
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#define ESPINTR_DSC 0x20 /* target disconnected, or timeout */
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#define ESPINTR_SVC 0x10 /* a device wants bus service */
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#define ESPINTR_CMP 0x08 /* function complete */
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#define ESPINTR_RSL 0x04 /* reselected */
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#define ESPINTR_SAT 0x02 /* selected with ATN */
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#define ESPINTR_SEL 0x01 /* selected (no ATN) */
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#define ESPINTR_BITS "\20\10SBR\7ILC\6DSC\5SVC\4CMP\3RSL\2SAT\1SEL"
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/*
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* Formula for select/reselect timeout (esp_timeout).
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* TU = 7682 * CCF * TCP
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* T / TU = register value
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* CCF = clock conversion factor
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* TCP = input clock period (in same units as T)
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* TU = time unit (i.e., the esp_timeout register counts in TUs)
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* T = desired timeout
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* (i.e., we want ceil(timeout / (7682*ccf*tcp))). If timeout is in ms.,
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* and tcp is in MHz, then (ccf * 7682)/tcp gives us 1000*TU, and
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* 1000*timeout/(1000*TU) gives us our result (but remember to round up).
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*
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* N.B.: The register value 0 gives a TU of 256.
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*/
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#define ESPTIMO_REGVAL(timo_ms, ccf, mhz) \
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howmany(1000 * (timo_ms), ((ccf) * 7682) / (mhz))
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/*
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* Value in esp_step. These tell us how much of a `sequence' completed,
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* and apply to the following sequenced operations:
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* [initiator]
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* select without ATN
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* select with ATN
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* select with ATN3
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* select with ATN and stop
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* [target]
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* bus-initiated select with ATN
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* bus-initiated select
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* receive command sequence
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* command complete sequence
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* disconnect sequence
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* terminate sequence
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* The actual values are too complicated to define here, except that
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* code 4 always means `everything worked and the command went out'
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* (and is thus typical for everything except ATN-and-stop).
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*/
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#define ESPSTEP_MASK 0x07 /* only these bits are valid */
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#define ESPSTEP_DONE 4 /* command went out */
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/*
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* Synchronous transfer period (esp_syncper, 5 bits).
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* The minimum clocks-per-period is 5 and the max is 35;
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* the default on reset is 5. Note that a period value of 4
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* actually gives 5 clocks.
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*/
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#define ESP_CLOCKS_TO_PERIOD(nclocks) ((nclocks) & 31)
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/*
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* Bits in fifo flags (esp_fflags) register. The FIFO itself
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* is only 16 bytes, so the byte count fits in 5 bits. Normally
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* a copy of the sequence step register appears in the top 3 bits,
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* but in test mode the chip re-uses one of those for a synchronous
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* offset bit.
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*/
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#define ESP_NFIFO(esp) ((esp)->esp_fflags & 0x1f)
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#define ESP_FFSTEP(esp) (((esp)->esp_fflags >> 5) & 3)
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#define ESPFFLAGS_TM_SOFFNZ 0x20 /* nonzero sync offset (test mode) */
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/*
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* Bits in esp_conf1.
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*/
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#define ESPCONF1_SLOW_CABLE 0x80 /* ``slow cable'' mode */
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#define ESPCONF1_REPORT 0x40 /* disable reporting of interrupts
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from scsi bus reset command */
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#define ESPCONF1_PARTST 0x20 /* parity test mode */
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#define ESPCONF1_PARENB 0x10 /* enable parity */
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#define ESPCONF1_TEST 0x08 /* chip test mode */
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#define ESPCONF1_ID_MASK 0x07 /* SCSI bus ID field */
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#define ESPCONF1_BITS "\20\10SLOW_CABLE\7REPORT\6PARTST\5PARENB\4TEST"
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/*
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* Values for clock conversion factor (esp_ccf).
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*/
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#define ESPCCF_FROMMHZ(mhz) (((mhz) + 4) / 5)
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#define ESPCCF_MIN 2 /* minimum CCF value */
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/*
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* Bits in esp_test (for board testing only; can only be used in test mode).
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*/
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#define ESPTEST_MBZ 0xf8 /* reserved; must be 0 */
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#define ESPTEST_TRISTATE 0x04 /* all output pins tristated */
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#define ESPTEST_INITIATOR 0x02 /* operate as initiator */
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#define ESPTEST_TARGET 0x01 /* operate as target */
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/*
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* Bits in esp_conf2.
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*/
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#define ESPCONF2_RSVD 0xe0 /* reserved */
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#define ESPCONF2_TRISTATE_DMA 0x10 /* tristate the DMA REQ pin */
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#define ESPCONF2_SCSI2 0x08 /* enable SCSI 2 (see p. 4-18) */
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#define ESPCONF2_TBPA 0x04 /* enable target bad parity abort */
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#define ESPCONF2_RPE 0x02 /* register parity ena (ESP2xx only) */
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#define ESPCONF2_DPE 0x01 /* DMA parity enable (ESP2xx only) */
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