249 lines
8.3 KiB
C
249 lines
8.3 KiB
C
/* $NetBSD: siisatareg.h,v 1.2 2008/09/08 23:36:54 gmcgarry Exp $ */
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/* Id: siisatareg.h,v 1.10 2008/05/21 15:51:36 jakllsch Exp */
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/*-
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* Copyright (c) 2007, 2008 Jonathan A. Kollasch.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/* Silicon Image SATA 2 controller register defines */
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#include <sys/cdefs.h>
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/* the SiI3124 has 4 ports, all others so far have less */
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#define SIISATA_MAX_PORTS 4
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/* the so far all parts have a full complement of slots */
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#define SIISATA_MAX_SLOTS 31
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/* structures */
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/* Scatter/Gather Entry */
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struct siisata_sge {
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#if 0
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uint32_t sge_dal; /* data address low */
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uint32_t sge_dah; /* " " high */
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#else
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uint64_t sge_da;
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#endif
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uint32_t sge_dc; /* data count (bytes) */
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uint32_t sge_flags; /* */
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#define SGE_FLAG_TRM __BIT(31)
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#define SGE_FLAG_LNK __BIT(30)
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#define SGE_FLAG_DRD __BIT(29)
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#define SGE_FLAG_XCF __BIT(28)
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} __packed;
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/* Scatter/Gather Table */
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/* must be aligned to 64-bit boundary */
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struct siisata_sgt {
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struct siisata_sge sgt_sge[4];
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} __packed;
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/* Port Request Block */
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struct siisata_prb {
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uint16_t prb_control; /* Control Field */
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#define PRB_CF_PROTOCOL_OVERRIDE __BIT(0)
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#define PRB_CF_RETRANSMIT __BIT(1)
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#define PRB_CF_EXTERNAL_COMMAND __BIT(2)
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#define PRB_CF_RECEIVE __BIT(3)
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#define PRB_CF_PACKET_READ __BIT(4)
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#define PRB_CF_PACKET_WRITE __BIT(5)
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#define PRB_CF_INTERRUPT_MASK __BIT(6)
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#define PRB_CF_SOFT_RESET __BIT(7)
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uint16_t prb_protocol_override;
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#define PRB_PO_PACKET __BIT(0)
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#define PRB_PO_LCQ __BIT(1)
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#define PRB_PO_NCQ __BIT(2)
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#define PRB_PO_READ __BIT(3)
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#define PRB_PO_WRITE __BIT(4)
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#define PRB_PO_TRANSPARENT __BIT(5)
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uint32_t prb_transfer_count;
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uint8_t prb_fis[20];
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uint32_t prb_reserved_0x1C; /* "must be zero" */
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/* First SGE in PRB is always reserved for ATAPI in this implementation. */
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uint8_t prb_atapi[16]; /* zero for non-ATAPI */
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struct siisata_sge prb_sge[1]; /* extended to NSGE */
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} __packed;
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#define SIISATA_NSGE ((MAXPHYS/PAGE_SIZE) + 1)
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#define SIISATA_CMD_ALIGN 0x7f
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#define SIISATA_CMD_SIZE \
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( ( sizeof(struct siisata_prb) + (SIISATA_NSGE - 1) * sizeof(struct siisata_sge) + SIISATA_CMD_ALIGN ) & ~SIISATA_CMD_ALIGN )
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/* PCI stuff */
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#define SIISATA_PCI_BAR0 0x10
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#define SIISATA_PCI_BAR1 0x18
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#define SIISATA_PCI_BAR2 0x20
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/* BAR 0 */
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/* port n slot status */
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#define GR_PXSS(n) (n*4)
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/* global control */
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#define GR_GC 0x40
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/* global interrupt status */
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#define GR_GIS 0x44
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/* phy config - don't touch */
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#define GR_PHYC 0x48
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/* BIST */
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#define GR_BIST_CONTROL 0x50
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#define GR_BIST_PATTERN 0x54
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#define GR_BIST_STATUS 0x58
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/* I2C SiI3132 */
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#define GR_SII3132_IICCONTROL 0x60
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#define GR_SII3132_IICSTATUS 0x64
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#define GR_SII3132_IICSLAVEADDR 0x68
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#define GR_SII3132_IICDATA 0x6c
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/* Flash */
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#define GR_FLSHADDR 0x70
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#define GR_FLSHDATA 0x74
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/* I2C SiI3124 */
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#define GR_SII3124_IICADDR 0x78
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#define GR_SII3124_IICDATA 0x7c
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/* GR_GC bits */
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#define GR_GC_GLBLRST __BIT(31)
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#define GR_GC_MSIACK __BIT(30)
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#define GR_GC_I2CINTEN __BIT(29)
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#define GR_GC_PERRRPTDSBL __BIT(28)
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#define GR_GC_3GBPS __BIT(24)
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#define GR_GC_REQ64 __BIT(20)
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#define GR_GC_DEVSEL __BIT(19)
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#define GR_GC_STOP __BIT(18)
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#define GR_GC_TRDY __BIT(17)
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#define GR_GC_M66EN __BIT(16)
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#define GR_GC_PXIE_MASK __BITS(SIISATA_MAX_PORTS - 1, 0)
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#define GR_GC_PXIE(n) __SHIFTIN(__BIT(n), GR_GC_PXIE_MASK)
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/* GR_GIS bits */
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#define GR_GIS_I2C __BIT(29)
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#define GR_GIS_PXIS_MASK __BITS(SIISATA_MAX_PORTS - 1, 0)
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#define GR_GIS_PXIS(n) __SHIFTIN(__BIT(n), GR_GIS_PXIS_MASK)
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/* BAR 1 */
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/* hmm, this could use a better name */
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#define PR_PORT_SIZE 0x2000
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#define PR_SLOT_SIZE 0x80
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/* get the register by port number and offset */
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#define PRO(p) (PR_PORT_SIZE * p)
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#define PRX(p,r) (PRO(p) + r)
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#define PRSX(p,s,o) (PRX(p, PR_SLOT_SIZE * s + o))
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#define PRSO_RTC 0x04 /* recieved transfer count */
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#define PRSO_FIS 0x08 /* base of FIS */
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#define PRO_PCS 0x1000 /* (write) port control set */
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#define PRO_PS PRO_PCS /* (read) port status */
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#define PRO_PCC 0x1004 /* port control clear */
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#define PRO_PIS 0x1008 /* port interrupt status */
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#define PRO_PIES 0x1010 /* port interrupt enable set */
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#define PRO_PIEC 0x1014 /* port interrupt enable clear */
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#define PRO_32BAUA 0x101c /* 32-bit activation upper address */
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#define PRO_PCEF 0x1020 /* port command execution fifo */
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#define PRO_PCE 0x1024 /* port command error */
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#define PRO_PFISC 0x1028 /* port FIS config */
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#define PRO_PCIRFIFOT 0x102c /* pci request fifo threshhold */
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#define PRO_P8B10BDEC 0x1040 /* port 8B/10B decode error counter */
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#define PRO_PCRCEC 0x1044 /* port crc error count */
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#define PRO_PHEC 0x1048 /* port handshake error count */
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#define PRO_PPHYC 0x1050 /* phy config */
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#define PRO_PSS 0x1800 /* port slot status */
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/* technically this is a shadow of the CAR */
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#define PRO_CAR 0x1c00
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#define PRO_CARX(p,s) (PRX(p, PRO_CAR) + s * sizeof(uint64_t))
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#define PRO_PCR 0x1e04 /* port context register */
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#define PRO_SCONTROL 0x1f00 /* SControl */
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#define PRO_SSTATUS 0x1f04 /* SStatus */
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#define PRO_SERROR 0x1f08 /* SError */
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#define PRO_SACTIVE 0x1f0c /* SActive */
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/* Port Command Error */
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#define PR_PCE_DEVICEERROR 1
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#define PR_PCE_SDBERROR 2
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#define PR_PCE_DATAFISERROR 3
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#define PR_PCE_SENDFISERROR 4
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#define PR_PCE_INCONSISTENTSTATE 5
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#define PR_PCE_DIRECTIONERROR 6
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#define PR_PCE_UNDERRUNERROR 7
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#define PR_PCE_OVERRUNERROR 8
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#define PR_PCE_LINKFIFOOVERRUN 9
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#define PR_PCE_PACKETPROTOCOLERROR 11
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#define PR_PCE_PLDSGTERRORBOUNDARY 16
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#define PR_PCE_PLDSGTERRORTARGETABORT 17
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#define PR_PCE_PLDSGTERRORMASTERABORT 18
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#define PR_PCE_PLDSGTERRORPCIPERR 19
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#define PR_PCE_PLDCMDERRORBOUNDARY 24
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#define PR_PCE_PLDCMDERRORTARGETABORT 25
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#define PR_PCE_PLDCMDERRORMASTERABORT 26
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#define PR_PCE_PLDCMDERRORPCIPERR 27
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#define PR_PCE_PSDERRORTARGETABORT 33
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#define PR_PCE_PSDERRORMASTERABORT 34
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#define PR_PCE_PSDERRORPCIPERR 35
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#define PR_PCE_SENDSERVICEERROROR 36
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#define PR_PIS_UNMASKED_SHIFT 16
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#define PR_PIS_CMDCMPL __BIT(0) /* command completion */
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#define PR_PIS_CMDERRR __BIT(1) /* command error */
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#define PR_PIS_PRTRDY __BIT(2) /* port ready */
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#define PR_PIS_PMCHNG __BIT(3) /* power management state change */
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#define PR_PIS_PHYRDYCHG __BIT(4)
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#define PR_PIS_COMWAKE __BIT(5)
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#define PR_PIS_UNRECFIS __BIT(6)
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#define PR_PIS_DEVEXCHG __BIT(7)
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#define PR_PIS_8B10BDET __BIT(8)
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#define PR_PIS_CRCET __BIT(9)
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#define PR_PIS_HET __BIT(10)
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#define PR_PIS_SDBN __BIT(11)
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#define PR_PC_PORT_RESET __BIT(0)
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#define PR_PC_DEVICE_RESET __BIT(1)
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#define PR_PC_PORT_INITIALIZE __BIT(2)
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#define PR_PC_INCOR __BIT(3)
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#define PR_PC_LED_DISABLE __BIT(4)
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#define PR_PC_PACKET_LENGTH __BIT(5)
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#define PR_PC_RESUME __BIT(6)
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#define PR_PC_TXBIST __BIT(7)
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#define PR_PC_CONT_DISABLE __BIT(8)
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#define PR_PC_SCRAMBLER_DISABLE __BIT(9)
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#define PR_PC_32BA __BIT(10)
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#define PR_PC_INTERLOCK_REJECT __BIT(11)
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#define PR_PC_INTERLOCK_ACCEPT __BIT(12)
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#define PR_PC_PMP_ENABLE __BIT(13)
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#define PR_PC_AIA __BIT(14)
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#define PR_PC_LED_ON __BIT(15)
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#define PR_PC_OOB_BYPASS __BIT(25)
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#define PR_PS_PORT_READY __BIT(31)
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#define PR_PSS_ATTENTION __BIT(31)
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#define PR_PSS_SLOT_MASK __BITS(30, 0)
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#define PR_PXSS(n) __SHIFTIN(__BIT(n), PR_PSS_SLOT_MASK)
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