272 lines
8.1 KiB
C
272 lines
8.1 KiB
C
/* $NetBSD: cpu.h,v 1.84 2008/02/27 18:26:16 xtraeme Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)cpu.h 8.4 (Berkeley) 1/5/94
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*/
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#ifndef _CPU_H_
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#define _CPU_H_
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */
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#define CPU_BOOTED_DEVICE 2 /* string: device booted from */
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#define CPU_BOOT_ARGS 3 /* string: args booted with */
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#define CPU_ARCH 4 /* integer: cpu architecture version */
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#define CPU_MAXID 5 /* number of valid machdep ids */
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#ifdef _KERNEL
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/*
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* Exported definitions unique to SPARC cpu support.
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*/
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#if defined(_KERNEL_OPT)
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#include "opt_multiprocessor.h"
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#include "opt_lockdebug.h"
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#include "opt_sparc_arch.h"
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#endif
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#include <machine/intr.h>
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#include <machine/psl.h>
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#include <sparc/sparc/cpuvar.h>
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#include <sparc/sparc/intreg.h>
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define curcpu() (cpuinfo.ci_self)
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#define curlwp (cpuinfo.ci_curlwp)
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#define CPU_IS_PRIMARY(ci) ((ci)->master)
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#define cpu_swapin(p) /* nothing */
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#define cpu_swapout(p) /* nothing */
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#define cpu_number() (cpuinfo.ci_cpuid)
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void cpu_proc_fork(struct proc *, struct proc *);
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#if defined(MULTIPROCESSOR)
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void cpu_boot_secondary_processors(void);
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#endif
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/*
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* Arguments to hardclock, softclock and statclock encapsulate the
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* previous machine state in an opaque clockframe. The ipl is here
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* as well for strayintr (see locore.s:interrupt and intr.c:strayintr).
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* Note that CLKF_INTR is valid only if CLKF_USERMODE is false.
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*/
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struct clockframe {
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u_int psr; /* psr before interrupt, excluding PSR_ET */
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u_int pc; /* pc at interrupt */
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u_int npc; /* npc at interrupt */
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u_int ipl; /* actual interrupt priority level */
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u_int fp; /* %fp at interrupt */
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};
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typedef struct clockframe clockframe;
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extern int eintstack[];
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#define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0)
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#define CLKF_LOPRI(framep,n) (((framep)->psr & PSR_PIL) < (n) << 8)
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#define CLKF_PC(framep) ((framep)->pc)
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#if defined(MULTIPROCESSOR)
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#define CLKF_INTR(framep) \
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((framep)->fp > (u_int)cpuinfo.eintstack - INT_STACK_SIZE && \
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(framep)->fp < (u_int)cpuinfo.eintstack)
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#else
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#define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack)
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#endif
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void sparc_softintr_init(void);
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/*
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* Preempt the current process on the target CPU if in interrupt from
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* user mode, or after the current trap/syscall if in system mode.
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*/
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#define cpu_need_resched(ci, flags) do { \
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(ci)->ci_want_resched = 1; \
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(ci)->ci_want_ast = 1; \
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\
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/* Just interrupt the target CPU, so it can notice its AST */ \
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if (((flags) & RESCHED_IMMED) || (ci)->ci_cpuid != cpu_number()) \
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XCALL0(sparc_noop, 1U << (ci)->ci_cpuid); \
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} while (/*CONSTCOND*/0)
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/*
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* Give a profiling tick to the current process when the user profiling
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* buffer pages are invalid. On the sparc, request an ast to send us
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* through trap(), marking the proc as needing a profiling tick.
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*/
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#define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, cpuinfo.ci_want_ast = 1)
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define cpu_signotify(l) do { \
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struct cpu_info *_ci = (l)->l_cpu; \
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_ci->ci_want_ast = 1; \
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\
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/* Just interrupt the target CPU, so it can notice its AST */ \
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if (_ci->ci_cpuid != cpu_number()) \
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XCALL0(sparc_noop, 1U << _ci->ci_cpuid); \
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} while (/*CONSTCOND*/0)
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/* CPU architecture version */
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extern int cpu_arch;
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/* Number of CPUs in the system */
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extern int sparc_ncpus;
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/*
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* Interrupt handler chains. Interrupt handlers should return 0 for
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* ``not me'' or 1 (``I took care of it''). intr_establish() inserts a
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* handler into the list. The handler is called with its (single)
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* argument, or with a pointer to a clockframe if ih_arg is NULL.
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*/
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extern struct intrhand {
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int (*ih_fun)(void *);
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void *ih_arg;
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struct intrhand *ih_next;
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int ih_classipl;
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} *intrhand[15];
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void intr_establish(int, int, struct intrhand *, void (*)(void));
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void intr_disestablish(int, struct intrhand *);
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void intr_lock_kernel(void);
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void intr_unlock_kernel(void);
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/* disksubr.c */
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struct dkbad;
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int isbad(struct dkbad *, int, int, int);
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/* machdep.c */
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int ldcontrolb(void *);
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void dumpconf(void);
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void * reserve_dumppages(void *);
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void wcopy(const void *, void *, u_int);
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void wzero(void *, u_int);
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/* clock.c */
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struct timeval;
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void lo_microtime(struct timeval *);
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void schedintr(void *);
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/* locore.s */
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struct fpstate;
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void savefpstate(struct fpstate *);
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void loadfpstate(struct fpstate *);
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int probeget(void *, int);
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void write_all_windows(void);
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void write_user_windows(void);
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void lwp_trampoline(void);
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struct pcb;
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void snapshot(struct pcb *);
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struct frame *getfp(void);
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int xldcontrolb(void *, struct pcb *);
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void copywords(const void *, void *, size_t);
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void qcopy(const void *, void *, size_t);
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void qzero(void *, size_t);
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/* trap.c */
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void kill_user_windows(struct lwp *);
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int rwindow_save(struct lwp *);
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/* cons.c */
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int cnrom(void);
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/* zs.c */
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void zsconsole(struct tty *, int, int, void (**)(struct tty *, int));
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#ifdef KGDB
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void zs_kgdb_init(void);
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#endif
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/* fb.c */
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void fb_unblank(void);
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/* kgdb_stub.c */
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#ifdef KGDB
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void kgdb_attach(int (*)(void *), void (*)(void *, int), void *);
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void kgdb_connect(int);
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void kgdb_panic(void);
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#endif
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/* emul.c */
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struct trapframe;
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int fixalign(struct lwp *, struct trapframe *);
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int emulinstr(int, struct trapframe *);
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/* cpu.c */
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void mp_pause_cpus(void);
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void mp_resume_cpus(void);
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void mp_halt_cpus(void);
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#ifdef DDB
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void mp_pause_cpus_ddb(void);
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void mp_resume_cpus_ddb(void);
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#endif
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/* intr.c */
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u_int setitr(u_int);
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u_int getitr(void);
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/*
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*
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* The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits
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* of the trap vector table. The next eight bits are supplied by the
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* hardware when the trap occurs, and the bottom four bits are always
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* zero (so that we can shove up to 16 bytes of executable code---exactly
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* four instructions---into each trap vector).
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*
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* The hardware allocates half the trap vectors to hardware and half to
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* software.
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*
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* Traps have priorities assigned (lower number => higher priority).
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*/
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struct trapvec {
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int tv_instr[4]; /* the four instructions */
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};
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extern struct trapvec *trapbase; /* the 256 vectors */
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#endif /* _KERNEL */
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#endif /* _CPU_H_ */
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