284 lines
9.7 KiB
C
284 lines
9.7 KiB
C
/* $NetBSD: gtidmareg.h,v 1.2 2005/02/27 00:27:21 perry Exp $ */
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/*
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* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Allegro Networks, Inc., and Wasabi Systems, Inc.
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* 4. The name of Allegro Networks, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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* 5. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
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* WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* idmareg.h - register & descriptor definitions for GT-64260 IDMA
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*
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* creation Wed Aug 15 08:58:37 PDT 2001 cliff
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*/
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#ifndef _IDMAREG_H
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#define _IDMAREG_H
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#define NIDMA_CHANS 8
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#define IDMA_BOUNDARY 1024*1024 /* boundary for bus_dmamap_create */
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#define IDMA_BIT(bitno) (1U << (bitno))
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#define IDMA_BITS(hi, lo) ((unsigned int)(~((~0ULL)<<((hi)+1)))&((~0)<<(lo)))
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#define IDMA_WORD_SHIFT 2 /* log2(sizeof(u_int32_t) */
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static volatile inline unsigned int
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idma_desc_read(u_int32_t *ip)
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{
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u_int32_t rv;
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asm volatile ("lwbrx %0,0,%1; eieio;"
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: "=r"(rv) : "r"(ip));
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return rv;
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}
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static volatile inline void
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idma_desc_write(u_int32_t *ip, u_int32_t val)
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{
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asm volatile ("stwbrx %0,0,%1; eieio;"
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:: "r"(val), "r"(ip));
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}
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typedef struct idma_desc {
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u_int32_t idd_ctl;
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u_int32_t idd_src_addr;
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u_int32_t idd_dst_addr;
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u_int32_t idd_next;
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u_int32_t idd_pad[4]; /* pad to CACHELINESIZE */
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} idma_desc_t __attribute__ ((aligned(CACHELINESIZE)));
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#define IDMA_DESC_CTL_CNT IDMA_BITS(23,0)
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#define IDMA_DESC_CTL_RES IDMA_BITS(29,24)
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#define IDMA_DESC_CTL_TERM IDMA_BIT(30)
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#define IDMA_DESC_CTL_OWN IDMA_BIT(31)
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#define IDMA_CH0_REG_OFF 0
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#define IDMA_CH4_REG_OFF 0x100
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#define IDMA_REG(chan, base) \
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((chan < 4) ? \
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((base) + ((chan) << IDMA_WORD_SHIFT)) : \
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(((base) + IDMA_CH4_REG_OFF) \
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+ (((chan) - 4) << IDMA_WORD_SHIFT)))
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#define IDMA_2X4_REG(chan, base) \
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(((chan) < 4) ? \
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(base) : \
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((base) + IDMA_CH4_REG_OFF))
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/*
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* IDMA Descriptor Registers
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*/
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#define IDMA_CNT_REG_BASE 0x800
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#define IDMA_CNT_REG(chan) IDMA_REG(chan, IDMA_CNT_REG_BASE)
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#define IDMA_SRC_REG_BASE 0x810
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#define IDMA_SRC_REG(chan) IDMA_REG(chan, IDMA_SRC_REG_BASE)
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#define IDMA_DST_REG_BASE 0x820
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#define IDMA_DST_REG(chan) IDMA_REG(chan, IDMA_DST_REG_BASE)
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#define IDMA_NXT_REG_BASE 0x830
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#define IDMA_NXT_REG(chan) IDMA_REG(chan, IDMA_NXT_REG_BASE)
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#define IDMA_CUR_REG_BASE 0x870
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#define IDMA_CUR_REG(chan) IDMA_REG(chan, IDMA_CUR_REG_BASE)
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#define IDMA_SRC_HIPCI_REG_BASE 0x890
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#define IDMA_SRC_HIPCI_REG(chan) \
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IDMA_REG(chan, IDMA_SRC_HIPCI_REG_BASE)
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#define IDMA_DST_HIPCI_REG_BASE 0x8a0
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#define IDMA_DST_HIPCI_REG(chan) \
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IDMA_REG(chan, IDMA_DST_HIPCI_REG_BASE)
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#define IDMA_NXT_HIPCI_REG_BASE 0x8b0
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#define IDMA_NXT_HIPCI_REG(chan) \
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IDMA_REG(chan, IDMA_NXT_HIPCI_REG_BASE)
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/*
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* IDMA Control Registers
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*/
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#define IDMA_CTLLO_REG_BASE 0x840
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#define IDMA_CTLLO_REG(chan) IDMA_REG(chan, IDMA_CTLLO_REG_BASE)
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#define IDMA_CTLHI_REG_BASE 0x880
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#define IDMA_CTLHI_REG(chan) IDMA_REG(chan, IDMA_CTLHI_REG_BASE)
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#define IDMA_ARB_REG_BASE 0x860
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#define IDMA_ARB_REG(chan) IDMA_2X4_REG(chan, IDMA_ARB_REG_BASE)
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#define IDMA_XTO_REG_BASE 0x8d0
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#define IDMA_XTO_REG(chan) IDMA_2X4_REG(chan, IDMA_XTO_REG_BASE)
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#define IDMA_CAUSE_REG_BASE 0x8c0
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#define IDMA_CAUSE_REG(chan) IDMA_2X4_REG(chan, IDMA_CAUSE_REG_BASE)
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#define IDMA_MASK_REG_BASE 0x8c4
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#define IDMA_MASK_REG(chan) IDMA_2X4_REG(chan, IDMA_MASK_REG_BASE)
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#define IDMA_EADDR_REG_BASE 0x8c8
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#define IDMA_EADDR_REG(chan) IDMA_2X4_REG(chan, IDMA_EADDR_REG_BASE)
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#define IDMA_ESEL_REG_BASE 0x8cc
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#define IDMA_ESEL_REG(chan) IDMA_2X4_REG(chan, IDMA_ESEL_REG_BASE)
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/*
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* IDMA Channel Control Lo bits
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*/
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#define IDMA_CTLLO_RESA IDMA_BITS(2,0)
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#define IDMA_CTLLO_SRCHOLD IDMA_BIT(3)
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#define IDMA_CTLLO_RESB IDMA_BIT(4)
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#define IDMA_CTLLO_DSTHOLD IDMA_BIT(5)
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#define IDMA_CTLLO_BURSTLIM IDMA_BITS(8,6)
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#define IDMA_CTLLO_BURST16 IDMA_BIT(6)
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#define IDMA_CTLLO_BURST32 IDMA_BITS(7,6)
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#define IDMA_CTLLO_BURST64 IDMA_BITS(8,6)
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#define IDMA_CTLLO_NOCHAIN IDMA_BIT(9)
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#define IDMA_CTLLO_INTR IDMA_BIT(10)
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#define IDMA_CTLLO_BLKMODE IDMA_BIT(11)
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#define IDMA_CTLLO_ENB IDMA_BIT(12)
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#define IDMA_CTLLO_FETCHND IDMA_BIT(13)
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#define IDMA_CTLLO_ACTIVE IDMA_BIT(14)
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#define IDMA_CTLLO_REQDIR IDMA_BIT(15)
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#define IDMA_CTLLO_REQMODE IDMA_BIT(16)
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#define IDMA_CTLLO_CDEN IDMA_BIT(17)
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#define IDMA_CTLLO_EOTEN IDMA_BIT(18)
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#define IDMA_CTLLO_EOTMODE IDMA_BIT(19)
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#define IDMA_CTLLO_ABORT IDMA_BIT(20)
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#define IDMA_CTLLO_SADDROVR IDMA_BITS(22,21)
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#define IDMA_CTLLO_DADDROVR IDMA_BITS(24,23)
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#define IDMA_CTLLO_NADDROVR IDMA_BITS(26,25)
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#define IDMA_CTLLO_ACKMODE IDMA_BIT(27)
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#define IDMA_CTLLO_TREQ IDMA_BIT(28)
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#define IDMA_CTLLO_ACKDIR IDMA_BITS(30,29)
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#define IDMA_CTLLO_DESCMODE IDMA_BIT(31)
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#define IDMA_CTLLO_RES \
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(IDMA_CTLHI_RESA|IDMA_CHN_CTLHI_RESB)
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#define IDMA_CTLL0_BURSTCODE(sz) (((sz) == 64) ? IDMA_CTLLO_BURST64 \
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: (((sz) == 32) ? IDMA_CTLLO_BURST32 \
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: (((sz) == 16) ? IDMA_CTLLO_BURST16 \
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: ~0)))
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/*
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* IDMA Channel Control Hi bits
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*/
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#define IDMA_CTLHI_RESA IDMA_BITS(3,0)
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#define IDMA_CTLHI_SRCPCISWAP IDMA_BITS(5,4)
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#define IDMA_CTLHI_SRCPCISWAP_NONE IDMA_BIT(4)
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#define IDMA_CTLHI_SRCSNOOP IDMA_BIT(6)
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#define IDMA_CTLHI_SRCPCI64 IDMA_BIT(7)
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#define IDMA_CTLHI_RESB IDMA_BITS(11,8)
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#define IDMA_CTLHI_DSTPCISWAP IDMA_BITS(13,12)
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#define IDMA_CTLHI_DSTPCISWAP_NONE IDMA_BIT(12)
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#define IDMA_CTLHI_DSTSNOOP IDMA_BIT(14)
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#define IDMA_CTLHI_DSTPCI64 IDMA_BIT(15)
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#define IDMA_CTLHI_RESC IDMA_BITS(19,16)
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#define IDMA_CTLHI_NXTPCISWAP IDMA_BITS(21,20)
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#define IDMA_CTLHI_NXTPCISWAP_NONE IDMA_BIT(20)
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#define IDMA_CTLHI_NXTSNOOP IDMA_BIT(22)
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#define IDMA_CTLHI_NXTPCI64 IDMA_BIT(23)
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#define IDMA_CTLHI_RESD IDMA_BITS(31,24)
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#define IDMA_CTLHI_RES \
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(IDMA_CTLHI_RESA|IDMA_CHN_CTLHI_RESB \
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|IDMA_CTLHI_RESC|IDMA_CHN_CTLHI_RESD)
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/*
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* IDMA Channel Arbiter Control bits
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*/
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#define IDMA_ARB_ARB_SHIFT 2
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#define IDMA_ARB_ARB_MASK(arb) \
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(BITS(1,0) << ((arb) << IDMA_ARB_ARB_SHIFT))
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/*
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* common IDMA Interrupt Register bits
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*/
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#define IDMA_INTR_COMP IDMA_BIT(0) /* completion */
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#define IDMA_INTR_MISS IDMA_BIT(1) /* failed addr decode */
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#define IDMA_INTR_ACCESS IDMA_BIT(2) /* access violation */
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#define IDMA_INTR_WPROT IDMA_BIT(3) /* write protect */
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#define IDMA_INTR_OWN IDMA_BIT(4) /* desc owner violation */
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#define IDMA_INTR_EOT IDMA_BIT(5) /* end of xfer */
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#define IDMA_INTR_RESX IDMA_BITS(7,6)
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#define IDMA_INTR_SHIFT 8
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#define IDMA_MASK_BITS IDMA_BITS(7,0)
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#define IDMA_INTR_BITS IDMA_BITS(5,0)
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#define IDMA_INTR_ERRS IDMA_BITS(5,1)
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#define IDMA_INTR_ALL_ERRS (IDMA_INTR_ERRS \
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|(IDMA_INTR_ERRS << IDMA_INTR_SHIFT) \
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|(IDMA_INTR_ERRS << (IDMA_INTR_SHIFT*2)) \
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|(IDMA_INTR_ERRS << (IDMA_INTR_SHIFT*3)))
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/*
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* IDMA Interrupt Cause Register bits
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*/
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#define IDMA_CAUSE_RES ( IDMA_INTR_RESX \
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|(IDMA_INTR_RESX << IDMA_INTR_SHIFT) \
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|(IDMA_INTR_RESX << (IDMA_INTR_SHIFT * 2)) \
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|(IDMA_INTR_RESX << (IDMA_INTR_SHIFT * 3)))
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/*
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* IDMA Interrupt Mask Register bits
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*/
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#define IDMA_MASK_SHIFT(chan) \
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(IDMA_INTR_SHIFT * ((chan < 4) ? chan : (chan - 4)))
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#define IDMA_MASK(chan, mask) \
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(((mask) & IDMA_MASK_BITS) << IDMA_MASK_SHIFT(chan))
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#define IDMA_MASK_RES (IDMA_MASK_RESX(0) \
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|IDMA_MASK_RESX(1) \
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|IDMA_MASK_RESX(2) \
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|IDMA_MASK_RESX(3))
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/*
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* IDMA Error Select Register bits
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*/
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#define IDMA_ESEL_MASK IDMA_BITS(4,0)
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#define IDMA_ESEL_RES IDMA_BITS(31,5)
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/*
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* IDMA Debug Registers
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*/
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#define IDMA_DBG_XADDR_REG_BASE 0x8e0
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#define IDMA_DBG_XADDR(xno) IDMA_2X4_REG(xno, IDMA_DBG_XADDR_REG_BASE)
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#define IDMA_DBG_XCMD_REG_BASE 0x8e4
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#define IDMA_DBG_XCMD(xno) IDMA_2X4_REG(xno, IDMA_DBG_XCMD_REG_BASE)
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#define IDMA_DBG_WDATLO_REG_BASE 0x8e8
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#define IDMA_DBG_WDATLO(xno) IDMA_2X4_REG(xno, IDMA_DBG_WDATLO_REG_BASE)
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#define IDMA_DBG_WDATHI_REG_BASE 0x8ec
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#define IDMA_DBG_WDATHI(xno) IDMA_2X4_REG(xno, IDMA_DBG_WDATHI_REG_BASE)
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#define IDMA_DBG_RDATLO_REG_BASE 0x8f0
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#define IDMA_DBG_RDATLO(xno) IDMA_2X4_REG(xno, IDMA_DBG_RDATLO_REG_BASE)
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#define IDMA_DBG_RDATHI_REG_BASE 0x8f4
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#define IDMA_DBG_RDATHI(xno) IDMA_2X4_REG(xno, IDMA_DBG_RDATHI_REG_BASE)
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#define IDMA_DBG_RID_REG_BASE 0x8fc
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#define IDMA_DBG_RID(xno) IDMA_2X4_REG(xno, IDMA_DBG_RID_REG_BASE)
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#endif /* _IDMAREG_H */
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