166 lines
6.1 KiB
C
166 lines
6.1 KiB
C
/* $NetBSD: igphyreg.h,v 1.1 2003/10/28 00:15:40 fvdl Exp $ */
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/*******************************************************************************
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Copyright (c) 2001-2003, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/*
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* Copied from the Intel code, and then modified to match NetBSD
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* style for MII registers more.
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*/
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/*
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* IGP01E1000 Specific Registers
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*/
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/* IGP01E1000 Specific Port Control Register - R/W */
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#define MII_IGPPHY_PORT_CONFIG 0x10 /* PHY specific config register */
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#define PSCR_AUTO_MDIX_PAR_DETECT 0x0010
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#define PSCR_PRE_EN 0x0020
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#define PSCR_SMART_SPEED 0x0080
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#define PSCR_DISABLE_TPLOOPBACK 0x0100
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#define PSCR_DISABLE_JABBER 0x0400
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#define PSCR_DISABLE_TRANSMIT 0x2000
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/* IGP01E1000 Specific Port Status Register - R/O */
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#define MII_IGPHY_PORT_STATUS 0x11
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#define PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
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#define PSSR_POLARITY_REVERSED 0x0002
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#define PSSR_CABLE_LENGTH 0x007C
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#define PSSR_FULL_DUPLEX 0x0200
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#define PSSR_LINK_UP 0x0400
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#define PSSR_MDIX 0x0800
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#define PSSR_SPEED_MASK 0xC000 /* speed bits mask */
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#define PSSR_SPEED_10MBPS 0x4000
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#define PSSR_SPEED_100MBPS 0x8000
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#define PSSR_SPEED_1000MBPS 0xC000
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#define PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
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#define PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
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/* IGP01E1000 Specific Port Control Register - R/W */
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#define MII_IGPHY_PORT_CTRL 0x12
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#define PSCR_TP_LOOPBACK 0x0001
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#define PSCR_CORRECT_NC_SCMBLR 0x0200
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#define PSCR_TEN_CRS_SELECT 0x0400
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#define PSCR_FLIP_CHIP 0x0800
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#define PSCR_AUTO_MDIX 0x1000
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#define PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
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/* IGP01E1000 Specific Port Link Health Register */
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#define MII_IGPHY_LINK_HEALTH 0x13
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#define PLHR_SS_DOWNGRADE 0x8000
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#define PLHR_GIG_SCRAMBLER_ERROR 0x4000
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#define PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
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#define PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
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#define PLHR_DATA_ERR_1 0x0200 /* LH */
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#define PLHR_DATA_ERR_0 0x0100
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#define PLHR_AUTONEG_FAULT 0x0010
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#define PLHR_AUTONEG_ACTIVE 0x0008
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#define PLHR_VALID_CHANNEL_D 0x0004
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#define PLHR_VALID_CHANNEL_C 0x0002
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#define PLHR_VALID_CHANNEL_B 0x0001
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#define PLHR_VALID_CHANNEL_A 0x0000
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/* IGP01E1000 GMII FIFO Register */
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#define MII_IGGMII_FIFO 0x14
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#define GMII_FLEX_SPD 0x10 /* Enable flexible speed */
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#define GMII_SPD 0x20 /* Enable SPD */
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/* IGP01E1000 Channel Quality Register */
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#define MII_IGPHY_CHANNEL_QUALITY 0x15
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#define MSE_CHANNEL_D 0x000F
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#define MSE_CHANNEL_C 0x00F0
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#define MSE_CHANNEL_B 0x0F00
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#define MSE_CHANNEL_A 0xF000
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#define MII_IGPHY_PAGE_SELECT 0x1F
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/* IGP01E1000 AGC Registers - stores the cable length values*/
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#define MII_IGPHY_AGC_A 0x1172
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#define MII_IGPHY_AGC_PARAM_A 0x1171
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#define MII_IGPHY_AGC_B 0x1272
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#define MII_IGPHY_AGC_PARAM_B 0x1271
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#define MII_IGPHY_AGC_C 0x1472
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#define MII_IGPHY_AGC_PARAM_C 0x1471
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#define MII_IGPHY_AGC_D 0x1872
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#define MII_IGPHY_AGC_PARAM_D 0x1871
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#define AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
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#define AGC_LENGTH_TABLE_SIZE 128
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#define AGC_RANGE 10
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/* IGP01E1000 DSP Reset Register */
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#define MII_IGPHY_DSP_RESET 0x1F33
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#define MII_IGPHY_DSP_SET 0x1F71
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#define MII_IGPHY_DSP_FFE 0x1F35
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#define MII_IGPHY_CHANNEL_NUM 4
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#define MII_IGPHY_EDAC_MU_INDEX 0xC000
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#define MII_IGPHY_EDAC_SIGN_EXT_9_BITS 0x8000
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#define MII_IGPHY_ANALOG_TX_STATE 0x2890
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#define MII_IGPHY_ANALOG_CLASS_A 0x2000
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#define MII_IGPHY_FORCE_ANALOG_ENABLE 0x0004
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#define MII_IGPHY_DSP_FFE_CM_CP 0x0069
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#define MII_IGPHY_DSP_FFE_DEFAULT 0x002A
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/* IGP01E1000 PCS Initialization register - stores the polarity status */
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#define MII_IGPHY_PCS_INIT_REG 0x00B4
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#define MII_IGPHY_PCS_CTRL_REG 0x00B5
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#define MII_IGPHY_ANALOG_REGS_PAGE 0x20C0
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#define PHY_POLARITY_MASK 0x0078
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/* IGP01E1000 Analog Register */
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#define MII_IGPHY_ANALOG_SPARE_FUSE_STATUS 0x20D1
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#define MII_IGPHY_ANALOG_FUSE_STATUS 0x20D0
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#define MII_IGPHY_ANALOG_FUSE_CONTROL 0x20DC
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#define MII_IGPHY_ANALOG_FUSE_BYPASS 0x20DE
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#define ANALOG_FUSE_POLY_MASK 0xF000
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#define ANALOG_FUSE_FINE_MASK 0x0F80
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#define ANALOG_FUSE_COARSE_MASK 0x0070
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#define ANALOG_SPARE_FUSE_ENABLED 0x0100
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#define ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
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#define ANALOG_FUSE_COARSE_THRESH 0x0040
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#define ANALOG_FUSE_COARSE_10 0x0010
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#define ANALOG_FUSE_FINE_1 0x0080
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#define ANALOG_FUSE_FINE_10 0x0500
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#define IGPHY_READ(sc, reg) \
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(PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, (reg) & ~0x1f), \
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PHY_READ(sc, (reg) & 0x1f))
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#define IGPHY_WRITE(sc, reg, val) \
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do { \
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PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, (reg) & ~0x1f); \
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PHY_WRITE(sc, (reg) & 0x1f, val); \
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} while (/*CONSTCOND*/0)
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#define IGPHY_TICK_DOWNSHIFT 3
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