48 lines
1.9 KiB
C
48 lines
1.9 KiB
C
/* $NetBSD: cpgreg.h,v 1.5 2002/04/28 17:10:34 uch Exp $ */
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/*-
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH3_CPGREG_H_
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#define _SH3_CPGREG_H_
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/*
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* Clock Pulse Generator
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*/
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#define SH3_FRQCR 0xffffff80 /* 16bit */
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#define SH4_FRQCR 0xffc00000 /* 16bit */
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/*
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* Standby Control
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*/
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#define SH3_STBCR 0xffffff82 /* 8bit */
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#define SH7709_STBCR2 0xffffff88 /* 8bit */
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#define SH4_STBCR 0xffc00004 /* 8bit */
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#define SH4_STBCR2 0xffc00010 /* 8bit */
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#endif /* !_SH3_CPGREG_H_ */
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