208 lines
6.8 KiB
C
208 lines
6.8 KiB
C
/* $NetBSD: grtworeg.h,v 1.1 2004/03/18 08:39:17 sekiya Exp $ */
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/*
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* Copyright (c) 2004 Christopher SEKIYA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* <<Id: LICENSE_GC,v 1.1 2001/10/01 23:24:05 cgd Exp>>
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*/
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#ifndef _ARCH_SGIMIPS_GIO_GRTWOREG_H_
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#define _ARCH_SGIMIPS_GIO_GRTWOREG_H_
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/*
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* Memory map:
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*
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* 0x1f000000 - 0x1f01ffff Shared data RAM
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* 0x1f020000 - 0x1f03ffff (unused)
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* 0x1f040000 - 0x1f05ffff FIFO
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* 0x1f060000 - 0x1f068000 HQ2 ucode
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* 0x1f068000 - 0x1f069fff GE7 (eight of them)
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* 0x1f06a000 - 0x1f06b004 HQ2
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* 0x1f06c000 Board revision register
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* 0x1f06c020 clock
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* 0x1f06c040 VC1
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* 0x1f06c060 BT479 Triple-DAC (read)
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* 0x1f06c080 BT479 Triple-DAC (write)
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* 0x1f06c0a0 BT457 DAC (red)
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* 0x1f06c0c0 BT457 DAC (green)
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* 0x1f06c0e0 BT457 DAC (blue)
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* 0x1f06c100 XMAP5 (five of them)
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* 0x1f06c1a0 XMAP5 ("xmap all")
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* 0x1f06c1c0 Kaleidoscope (AB1)
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* 0x1f06c1e0 Kaleidoscope (CC1)
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* 0x1f06c200 RE3 (27-bit registers)
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* 0x1f06c280 RE3 (24-bit registers)
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* 0x1f06c600 RE3 (32-bit registers)
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*/
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#define GR2_FIFO 0x40000
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#define GR2_FIFO_INIT (GR2_FIFO + 0x644)
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#define GR2_FIFO_COLOR (GR2_FIFO + 0x648)
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#define GR2_FIFO_FINISH (GR2_FIFO + 0x64c)
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#define GR2_FIFO_PNT2I (GR2_FIFO + 0x650)
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#define GR2_FIFO_RECTI2D (GR2_FIFO + 0x654)
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#define GR2_FIFO_CMOV2I (GR2_FIFO + 0x658)
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#define GR2_FIFO_LINE2I (GR2_FIFO + 0x65c)
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#define GR2_FIFO_DRAWCHAR (GR2_FIFO + 0x660)
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#define GR2_FIFO_RECTCOPY (GR2_FIFO + 0x664)
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#define GR2_FIFO_DATA (GR2_FIFO + 0x77c)
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/* HQ2 */
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#define HQ2_BASE 0x6a000
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#define HQ2_ATTRJUMP (HQ2_BASE + 0x00)
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#define HQ2_VERSION (HQ2_BASE + 0x40)
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#define HQ2_VERSION_MASK 0xff000000
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#define HQ2_VERSION_SHIFT 23
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#define HQ2_NUMGE (HQ2_BASE + 0x44)
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#define HQ2_FIN1 (HQ2_BASE + 0x48)
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#define HQ2_FIN2 (HQ2_BASE + 0x4c)
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#define HQ2_DMASYNC (HQ2_BASE + 0x50)
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#define HQ2_FIFO_FULL_TIMEOUT (HQ2_BASE + 0x54)
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#define HQ2_FIFO_EMPTY_TIMEOUT (HQ2_BASE + 0x58)
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#define HQ2_FIFO_FULL (HQ2_BASE + 0x5c)
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#define HQ2_FIFO_EMPTY (HQ2_BASE + 0x60)
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#define HQ2_GE7_LOAD_UCODE (HQ2_BASE + 0x64)
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#define HQ2_GEDMA (HQ2_BASE + 0x68)
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#define HQ2_HQ_GEPC (HQ2_BASE + 0x6c)
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#define HQ2_GEPC (HQ2_BASE + 0x70)
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#define HQ2_INTR (HQ2_BASE + 0x74)
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#define HQ2_UNSTALL (HQ2_BASE + 0x78)
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#define HQ2_MYSTERY (HQ2_BASE + 0x7c) /* == 0xdeadbeef */
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#define HQ2_REFRESH (HQ2_BASE + 0x80)
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#define HQ2_FIN3 (HQ2_BASE + 0x100)
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/* GE7 */
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#define GE7_REVISION 0x680fc
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#define GE7_REVISION_MASK 0xf0
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/* VC1 */
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#define VC1_BASE 0x6c040
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#define VC1_COMMAND (VC1_BASE + 0x00)
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#define VC1_XMAPMODE (VC1_BASE + 0x04)
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#define VC1_SRAM (VC1_BASE + 0x08)
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#define VC1_TESTREG (VC1_BASE + 0x0c)
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#define VC1_ADDRLO (VC1_BASE + 0x10)
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#define VC1_ADDRHI (VC1_BASE + 0x14)
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#define VC1_SYSCTL (VC1_BASE + 0x18)
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/* VC1 System Control Register */
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#define VC1_SYSCTL_INTERRUPT 0x01
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#define VC1_SYSCTL_VTG 0x02
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#define VC1_SYSCTL_VC1 0x04
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#define VC1_SYSCTL_DID 0x08
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#define VC1_SYSCTL_CURSOR 0x10
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#define VC1_SYSCTL_CURSOR_DISPLAY 0x20
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#define VC1_SYSCTL_GENSYNC 0x40
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#define VC1_SYSCTL_VIDEO 0x80
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/* VC1 SRAM memory map */
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#define VC1_SRAM_VIDTIM_LST_BASE 0x0000
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#define VC1_SRAM_VIDTIM_CURSLST_BASE 0x0400
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#define VC1_SRAM_VIDTIM_FRMT_BASE 0x0800
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#define VC1_SRAM_VIDTIM_CURSFRMT_BASE 0x0900
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#define VC1_SRAM_INTERLACED 0x09f0
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#define VC1_SRAM_SCREENWIDTH 0x09f2
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#define VC1_SRAM_NEXTDID_ADDR 0x09f4
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#define VC1_SRAM_CURSOR0_BASE 0x0a00 /* 32x32 */
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#define VC1_SRAM_DID_FRMT_BASE 0x0b00
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#define VC1_SRAM_DID_MAX_FMTSIZE 0x0900
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#define VC1_SRAM_DID_LST_END 0x8000
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/* VC1 registers */
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#define VC1_VIDEO_EP 0x00
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#define VC1_VIDEO_LC 0x02
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#define VC1_VIDEO_SC 0x04
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#define VC1_VIDEO_TSA 0x06
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#define VC1_VIDEO_TSB 0x07
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#define VC1_VIDEO_TSC 0x08
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#define VC1_VIDEO_LP 0x09
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#define VC1_VIDEO_LS_EP 0x0b
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#define VC1_VIDEO_LR 0x0d
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#define VC1_VIDEO_FC 0x10
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#define VC1_VIDEO_ENABLE 0x14
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/* Cursor Generator */
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#define VC1_CURSOR_EP 0x20
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#define VC1_CURSOR_XL 0x22
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#define VC1_CURSOR_YL 0x24
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#define VC1_CURSOR_MODE 0x26
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#define VC1_CURSOR_BX 0x27
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#define VC1_CURSOR_LY 0x28
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#define VC1_CURSOR_YC 0x2a
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#define VC1_CURSOR_CC 0x2e
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#define VC1_CURSOR_RC 0x30
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/* Board revision register */
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#define GR2_REVISION 0x6c000
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#define GR2_REVISION_RD0 0x6c000
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#define GR2_REVISION_RD0_VERSION_MASK 0x0f
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#define GR2_REVISION4_RD0_MONITOR_MASK 0xf0
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#define GR2_REVISION_RD1 0x6c004
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#define GR2_REVISION_RD1_BACKEND_REV 0x03
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#define GR2_REVISION_RD1_ZBUFFER 0x0c
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#define GR2_REVISION4_RD1_BACKEND 0x03
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#define GR2_REVISION4_RD1_24BPP 0x10
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#define GR2_REVISION4_RD1_ZBUFFER 0x20
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#define GR2_REVISION_RD2 0x6c008
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#define GR2_REVISION_RD2_BACKEND_REV 0x000c
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/* one slot = 8bpp, two slots = 16bpp, three slots = 24bpp, br < 4 only */
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#define GR2_REVISION_RD3 0x6c00c
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#define GR2_REVISION_RD3_VMA 0x03 /* both bits set == empty
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* slot */
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#define GR2_REVISION_RD3_VMB 0x0c
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#define GR2_REVISION_RD3_VMC 0x30
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/* XMAP5 -- five of them, 0x1f06c100 - 0x1f06c1a0 */
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#define XMAP5_MISC 0x00
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#define XMAP5_MODE 0x04
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#define XMAP5_CLUT 0x08
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#define XMAP5_CRC 0x0c
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#define XMAP5_ADDRLO 0x10
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#define XMAP5_ADRHI 0x14
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#define XMAP5_BYTECOUNT 0x18
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#define XMAP5_FIFOSTATUS 0x1c
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#define XMAPALL_MISC 0x6c1a0
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#define XMAPALL_MODE 0x6c1a4
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#define XMAPALL_CLUT 0x6c1a8
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#define XMAPALL_CRC 0x6c1ac
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#define XMAPALL_ADDRLO 0x6c190
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#define XMAPALL_ADDRHI 0x6c194
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#define XMAPALL_BYTECOUNT 0x6c198
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#define XMAPALL_FIFOSTATUS 0x6c19c
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#endif
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