338 lines
7.9 KiB
ArmAsm
338 lines
7.9 KiB
ArmAsm
/*-
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* Copyright (c) 1993, 1994 Charles Hannum.
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* Copyright (c) 1989, 1990 William F. Jolitz.
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)icu.s 7.2 (Berkeley) 5/21/91
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* $Id: icu.s,v 1.27 1994/03/25 00:45:42 mycroft Exp $
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*/
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/*
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* AT/386
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* Vector interrupt control section
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*/
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#include <net/netisr.h>
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/*
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* All spl levels include astmask; this forces cpl to be non-zero when
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* splx()ing from nested spl levels, and thus soft interrupts do not
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* get executed. Logically, all spl levels are `above' soft interupts.
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*/
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#ifdef notyet
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#include "sio.h"
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#else
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#define NSIO 0
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#endif
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.data
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.globl _cpl
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_cpl:
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.long -1 # current priority (all off)
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.globl _highmask
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_highmask:
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.long -1 # XXX needed for braindead config
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.globl _ipending
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_ipending:
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.long 0
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.globl _imen
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_imen:
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.long 0xffff # interrupt mask enable (all off)
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.globl _clockmask
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_clockmask:
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.long 1
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.globl _ttymask
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_ttymask:
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.long 0
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.globl _biomask
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_biomask:
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.long 0
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.globl _netmask
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_netmask:
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.long 0
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.globl _impmask
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_impmask:
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.long 0
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.globl _astmask
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_astmask:
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.long 0x80000000
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vec:
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.long INTRLOCAL(vec0), INTRLOCAL(vec1), INTRLOCAL(vec2)
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.long INTRLOCAL(vec3), INTRLOCAL(vec4), INTRLOCAL(vec5)
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.long INTRLOCAL(vec6), INTRLOCAL(vec7), INTRLOCAL(vec8)
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.long INTRLOCAL(vec9), INTRLOCAL(vec10), INTRLOCAL(vec11)
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.long INTRLOCAL(vec12), INTRLOCAL(vec13), INTRLOCAL(vec14)
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.long INTRLOCAL(vec15)
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#define GENSPL(name, mask, event) \
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.globl _spl/**/name ; \
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ALIGN_TEXT ; \
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_spl/**/name: ; \
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movl _cpl,%eax ; \
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movl %eax,%edx ; \
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orl mask,%edx ; \
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movl %edx,_cpl ; \
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ret
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#define FASTSPL(mask) \
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movl mask,_cpl
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#define FASTSPL_VARMASK(varmask) \
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movl varmask,%eax ; \
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movl %eax,_cpl
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.text
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ALIGN_TEXT
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INTRLOCAL(unpend_v):
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bsfl %eax,%eax # slow, but not worth optimizing
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btrl %eax,_ipending
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jnc INTRLOCAL(unpend_v_next) # some intr cleared the in-memory bit
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movl Vresume(,%eax,4),%eax
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testl %eax,%eax
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jz INTRLOCAL(noresume)
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jmp %eax
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ALIGN_TEXT
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/*
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* XXX - must be some fastintr, need to register those too.
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*/
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INTRLOCAL(noresume):
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#if NSIO > 0
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call _softsio1
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#endif
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INTRLOCAL(unpend_v_next):
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movl _cpl,%eax
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movl %eax,%edx
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notl %eax
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andl _ipending,%eax
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jz INTRLOCAL(none_to_unpend)
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jmp INTRLOCAL(unpend_v)
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/*
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* Handle return from interrupt after device handler finishes
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*/
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ALIGN_TEXT
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doreti:
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addl $4,%esp # discard unit arg
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popl %eax # get previous priority
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/*
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* Now interrupt frame is a trap frame!
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*
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* XXX - setting up the interrupt frame to be almost a stack frame is mostly
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* a waste of time.
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*/
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movl %eax,_cpl
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movl %eax,%edx
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notl %eax
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andl _ipending,%eax
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jnz INTRLOCAL(unpend_v)
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INTRLOCAL(none_to_unpend):
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testl %edx,%edx # returning to zero priority?
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jz 2f
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INTRFASTEXIT
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.globl _netisr,_sir
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#define DONET(s, c, event) ; \
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.globl c ; \
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btrl $s,_netisr ; \
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jnc 1f ; \
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call c ; \
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1:
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ALIGN_TEXT
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2:
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/*
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* XXX - might need extra locking while testing reg copy of netisr, but
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* interrupt routines setting it would not cause any new problems (since we
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* don't loop, fresh bits will not be processed until the next doreti or spl0)
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*/
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btrl $SIR_NET,_sir
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jnc test_clock
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FASTSPL_VARMASK(_netmask)
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DONET(NETISR_RAW, _rawintr, 5)
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#ifdef INET
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DONET(NETISR_IP, _ipintr, 6)
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#endif
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#ifdef IMP
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DONET(NETISR_IMP, _impintr, 7)
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#endif
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#ifdef NS
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DONET(NETISR_NS, _nsintr, 8)
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#endif
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#ifdef ISO
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DONET(NETISR_ISO, _clnlintr, 25)
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#endif
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FASTSPL($0)
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test_clock:
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btrl $SIR_CLOCK,_sir
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jnc test_ast
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FASTSPL_VARMASK(_astmask)
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pushl $0 # XXX previous cpl (probably not used)
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pushl $0x7f # XXX dummy unit number
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pushl %esp
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call _softclock
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addl $12,%esp # XXX discard dummies
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FASTSPL($0)
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test_ast:
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testb $SEL_RPL_MASK,TF_CS(%esp)
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jz 1f
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btrl $SIR_AST,_sir
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jnc 1f
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/* Pushed T_ASTFLT into TF_TRAPNO on interrupt entry. */
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call _trap
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1:
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INTRFASTEXIT
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/*
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* Interrupt priority mechanism
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* -- soft splXX masks with group mechanism (cpl)
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* -- h/w masks for currently active or unused interrupts (imen)
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* -- ipending = active interrupts currently masked by cpl
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*/
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GENSPL(tty, _ttymask, 18)
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GENSPL(bio, _biomask, 12)
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GENSPL(net, _netmask, 16)
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GENSPL(imp, _impmask, 15)
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GENSPL(high, $-1, 14)
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GENSPL(clock, _clockmask, 13)
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GENSPL(softclock, _astmask, 17)
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.globl _spl0
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ALIGN_TEXT
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_spl0:
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in_spl0:
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movl _cpl,%eax
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pushl %eax # save old priority
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btrl $SIR_NET,_sir
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jnc INTRLOCAL(over_net_stuff_for_spl0)
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FASTSPL_VARMASK(_netmask)
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DONET(NETISR_RAW, _rawintr, 20)
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#ifdef INET
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DONET(NETISR_IP, _ipintr, 21)
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#endif
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#ifdef IMP
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DONET(NETISR_IMP, _impintr, 26)
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#endif
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#ifdef NS
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DONET(NETISR_NS, _nsintr, 27)
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#endif
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#ifdef ISO
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DONET(NETISR_ISO, _clnlintr, 28)
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#endif
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INTRLOCAL(over_net_stuff_for_spl0):
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FASTSPL($0)
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movl _ipending,%eax
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testl %eax,%eax
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jnz INTRLOCAL(unpend_V)
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popl %eax # return old priority
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ret
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.globl _splx
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ALIGN_TEXT
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_splx:
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movl 4(%esp),%eax # new priority
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testl %eax,%eax
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jz in_spl0 # going to "zero level" is special
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pushl _cpl # save old priority
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movl %eax,_cpl # set new priority
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notl %eax
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andl _ipending,%eax
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jnz INTRLOCAL(unpend_V)
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popl %eax # return old priority
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ret
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ALIGN_TEXT
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INTRLOCAL(unpend_V):
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bsfl %eax,%eax
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btrl %eax,_ipending
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jnc INTRLOCAL(unpend_V_next)
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movl Vresume(,%eax,4),%edx
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testl %edx,%edx
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jz INTRLOCAL(noresumeV)
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/*
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* We would prefer to call the intr handler directly here but that doesn't
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* work for badly behaved handlers that want the interrupt frame. Also,
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* there's a problem determining the unit number. We should change the
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* interface so that the unit number is not determined at config time.
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*/
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jmp *vec(,%eax,4)
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ALIGN_TEXT
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/*
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* XXX - must be some fastintr, need to register those too.
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*/
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INTRLOCAL(noresumeV):
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#if NSIO > 0
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call _softsio1
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#endif
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INTRLOCAL(unpend_V_next):
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movl _cpl,%eax
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notl %eax
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andl _ipending,%eax
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jnz INTRLOCAL(unpend_V)
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popl %eax
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ret
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#define BUILD_VEC(irq_num) \
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ALIGN_TEXT ; \
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INTRLOCAL(vec/**/irq_num): ; \
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int $(ICU_OFFSET + irq_num) ; \
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popl %eax ; \
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ret
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BUILD_VEC(0)
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BUILD_VEC(1)
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BUILD_VEC(2)
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BUILD_VEC(3)
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BUILD_VEC(4)
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BUILD_VEC(5)
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BUILD_VEC(6)
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BUILD_VEC(7)
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BUILD_VEC(8)
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BUILD_VEC(9)
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BUILD_VEC(10)
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BUILD_VEC(11)
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BUILD_VEC(12)
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BUILD_VEC(13)
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BUILD_VEC(14)
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BUILD_VEC(15)
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