171 lines
5.8 KiB
C
171 lines
5.8 KiB
C
/* $NetBSD: mipsNN.h,v 1.3 2003/02/07 17:38:48 cgd Exp $ */
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/*
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* Copyright 2000, 2001
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* Broadcom Corporation. All rights reserved.
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*
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* This software is furnished under license and may be used and copied only
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* in accordance with the following terms and conditions. Subject to these
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* conditions, you may download, copy, install, use, modify and distribute
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* modified or unmodified copies of this software in source and/or binary
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* form. No title or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce and
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* retain this copyright notice and list of conditions as they appear in
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* the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or logo of
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* Broadcom Corporation. The "Broadcom Corporation" name may not be
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* used to endorse or promote products derived from this software
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* without the prior written permission of Broadcom Corporation.
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*
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* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
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* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
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* FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
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* LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Values related to the MIPS32/MIPS64 Privileged Resource Architecture.
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*/
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#define _MIPSNN_SHIFT(reg) __MIPSNN_SHIFT(reg)
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#define __MIPSNN_SHIFT(reg) MIPSNN_ ## reg ## _SHIFT
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#define _MIPSNN_MASK(reg) __MIPSNN_MASK(reg)
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#define __MIPSNN_MASK(reg) MIPSNN_ ## reg ## _MASK
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#define MIPSNN_GET(reg, x) \
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((unsigned)((x) & _MIPSNN_MASK(reg)) >> _MIPSNN_SHIFT(reg))
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#define MIPSNN_PUT(reg, val) \
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(((x) << _MIPSNN_SHIFT(reg)) & _MIPSNN_MASK(reg))
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/*
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* Values in Configuration Register (CP0 Register 16, Select 0)
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*/
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/* "M" (R): Configuration Register 1 present if set. Defined as always set. */
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#define MIPSNN_CFG_M 0x80000000
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/* Reserved for CPU implementations. */
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// reserved 0x7fff0000
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/* "BE" (R): Big endian if set, little endian if clear. */
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#define MIPSNN_CFG_BE 0x00008000
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/* "AT" (R): architecture type implemented by processor */
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#define MIPSNN_CFG_AT_MASK 0x00006000
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#define MIPSNN_CFG_AT_SHIFT 13
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#define MIPSNN_CFG_AT_MIPS32 0 /* MIPS32 */
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#define MIPSNN_CFG_AT_MIPS64S 1 /* MIPS64S */
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#define MIPSNN_CFG_AT_MIPS64 2 /* MIPS64 */
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// reserved 3
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/* "AR" (R): Architecture revision level implemented by proc. */
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#define MIPSNN_CFG_AR_MASK 0x00001c00
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#define MIPSNN_CFG_AR_SHIFT 10
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#define MIPSNN_CFG_AR_REV1 0 /* Revision 1 */
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// reserved other values
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/* "MT" (R): MMU type implemented by processor */
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#define MIPSNN_CFG_MT_MASK 0x00000380
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#define MIPSNN_CFG_MT_SHIFT 7
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#define MIPSNN_CFG_MT_NONE 0 /* No MMU */
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#define MIPSNN_CFG_MT_TLB 1 /* Std TLB */
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#define MIPSNN_CFG_MT_BAT 2 /* Std BAT */
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#define MIPSNN_CFG_MT_FIXED 3 /* Std Fixed mapping */
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// reserved other values
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/* Reserved. Write as 0, reads as 0. */
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// reserved 0x00000070
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/* "M" (R): Virtual instruction cache if set. */
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#define MIPSNN_CFG_VI 0x00000008
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/* "K0" (RW): Kseg0 coherency algorithm. (values are TLB_ATTRs) */
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#define MIPSNN_CFG_K0_MASK 0x00000007
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#define MIPSNN_CFG_K0_SHIFT 0
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/*
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* Values in Configuration Register 1 (CP0 Register 16, Select 1)
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*/
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/* Reserved for Configuration Register 2 present. Write as 0, reads as 0. */
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// reserved 0x80000000
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/* MS (R): Number of TLB entries - 1. */
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#define MIPSNN_CFG1_MS_MASK 0x7e000000
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#define MIPSNN_CFG1_MS_SHIFT 25
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#define MIPSNN_CFG1_MS(x) (MIPSNN_GET(CFG1_MS, (x)) + 1)
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/* "IS" (R): (Primary) I-cache sets per way. */
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#define MIPSNN_CFG1_IS_MASK 0x01c00000
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#define MIPSNN_CFG1_IS_SHIFT 22
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#define MIPSNN_CFG1_IS_RSVD 7 /* rsvd value, otherwise: */
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#define MIPSNN_CFG1_IS(x) (64 << MIPSNN_GET(CFG1_IS, (x)))
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/* "IL" (R): (Primary) I-cache line size. */
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#define MIPSNN_CFG1_IL_MASK 0x00380000
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#define MIPSNN_CFG1_IL_SHIFT 19
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#define MIPSNN_CFG1_IL_NONE 0 /* No I-cache, */
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#define MIPSNN_CFG1_IL_RSVD 7 /* rsvd value, otherwise: */
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#define MIPSNN_CFG1_IL(x) (2 << MIPSNN_GET(CFG1_IL, (x)))
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/* "IA" (R): (Primary) I-cache associativity (ways - 1). */
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#define MIPSNN_CFG1_IA_MASK 0x00070000
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#define MIPSNN_CFG1_IA_SHIFT 16
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#define MIPSNN_CFG1_IA(x) MIPSNN_GET(CFG1_IA, (x))
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/* "DS" (R): (Primary) D-cache sets per way. */
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#define MIPSNN_CFG1_DS_MASK 0x0000e000
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#define MIPSNN_CFG1_DS_SHIFT 13
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#define MIPSNN_CFG1_DS_RSVD 7 /* rsvd value, otherwise: */
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#define MIPSNN_CFG1_DS(x) (64 << MIPSNN_GET(CFG1_DS, (x)))
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/* "DL" (R): (Primary) D-cache line size. */
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#define MIPSNN_CFG1_DL_MASK 0x00001c00
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#define MIPSNN_CFG1_DL_SHIFT 10
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#define MIPSNN_CFG1_DL_NONE 0 /* No D-cache, */
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#define MIPSNN_CFG1_DL_RSVD 7 /* rsvd value, otherwise: */
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#define MIPSNN_CFG1_DL(x) (2 << MIPSNN_GET(CFG1_DL, (x)))
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/* "DA" (R): (Primary) D-cache associativity (ways - 1). */
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#define MIPSNN_CFG1_DA_MASK 0x00000380
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#define MIPSNN_CFG1_DA_SHIFT 7
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#define MIPSNN_CFG1_DA(x) MIPSNN_GET(CFG1_DA, (x))
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/* Reserved. Write as 0, reads as 0. */
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// reserved 0x00000060
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/* "PC" (R): Performance Counters implemented if set. */
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#define MIPSNN_CFG1_PC 0x00000010
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/* "WR" (R): Watch registers implemented if set. */
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#define MIPSNN_CFG1_WR 0x00000008
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/* "CA" (R): Code compressiong (MIPS16) implemented if set. */
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#define MIPSNN_CFG1_CA 0x00000004
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/* "EP" (R): EJTAG implemented if set. */
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#define MIPSNN_CFG1_EP 0x00000002
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/* "FP" (R): FPU implemented if set. */
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#define MIPSNN_CFG1_FP 0x00000001
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