177 lines
6.4 KiB
C
177 lines
6.4 KiB
C
/* $NetBSD: cache_tx39.h,v 1.4 2003/02/17 11:35:03 simonb Exp $ */
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/*-
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* Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi; and by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Cache definitions/operations for TX3900-style caches.
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*
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* XXX THIS IS NOT YET COMPLETE.
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*/
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#define CACHE_TX39_I 0
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#define CACHE_TX39_D 1
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#define CACHEOP_TX3900_INDEX_INV (0 << 2) /* I */
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#define CACHEOP_TX3900_ILRUC (1 << 2) /* I, D */
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#define CACHEOP_TX3900_ILCKC (2 << 2) /* D */
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#define CACHEOP_TX3900_HIT_INV (4 << 2) /* D */
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#define CACHEOP_TX3920_INDEX_INV CACHEOP_TX3900_INDEX_INV
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#define CACHEOP_TX3920_INDEX_WB_INV (0 << 2) /* D */
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#define CACHEOP_TX3920_ILRUC CACHEOP_TX3900_ILRUC
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#define CACHEOP_TX3920_INDEX_LOAD_TAG (3 << 2) /* I, D */
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#define CACHEOP_TX3920_HIT_INV (4 << 2) /* I, D */
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#define CACHEOP_TX3920_HIT_WB_INV (5 << 2) /* D */
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#define CACHEOP_TX3920_HIT_WB (6 << 2) /* D */
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#define CACHEOP_TX3920_ISTTAG (7 << 2) /* I, D */
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#if !defined(_LOCORE)
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/*
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* cache_tx39_op_line:
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*
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* Perform the specified cache operation on a single line.
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*/
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#define cache_op_tx39_line(va, op) \
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do { \
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__asm __volatile( \
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".set noreorder \n\t" \
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".set push \n\t" \
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".set mips3 \n\t" \
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"cache %1, 0(%0) \n\t" \
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".set pop \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory"); \
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} while (/*CONSTCOND*/0)
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/*
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* cache_tx39_op_32lines_4:
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*
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* Perform the specified cache operation on 32 4-byte
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* cache lines.
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*/
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#define cache_tx39_op_32lines_4(va, op) \
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do { \
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__asm __volatile( \
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".set noreorder \n\t" \
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".set push \n\t" \
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".set mips3 \n\t" \
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"cache %1, 0x00(%0); cache %1, 0x04(%0); \n\t" \
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"cache %1, 0x08(%0); cache %1, 0x0c(%0); \n\t" \
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"cache %1, 0x10(%0); cache %1, 0x14(%0); \n\t" \
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"cache %1, 0x18(%0); cache %1, 0x1c(%0); \n\t" \
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"cache %1, 0x20(%0); cache %1, 0x24(%0); \n\t" \
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"cache %1, 0x28(%0); cache %1, 0x2c(%0); \n\t" \
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"cache %1, 0x30(%0); cache %1, 0x34(%0); \n\t" \
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"cache %1, 0x38(%0); cache %1, 0x3c(%0); \n\t" \
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"cache %1, 0x40(%0); cache %1, 0x44(%0); \n\t" \
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"cache %1, 0x48(%0); cache %1, 0x4c(%0); \n\t" \
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"cache %1, 0x50(%0); cache %1, 0x54(%0); \n\t" \
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"cache %1, 0x58(%0); cache %1, 0x5c(%0); \n\t" \
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"cache %1, 0x60(%0); cache %1, 0x64(%0); \n\t" \
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"cache %1, 0x68(%0); cache %1, 0x6c(%0); \n\t" \
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"cache %1, 0x70(%0); cache %1, 0x74(%0); \n\t" \
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"cache %1, 0x78(%0); cache %1, 0x7c(%0); \n\t" \
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".set pop \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory"); \
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} while (/*CONSTCOND*/0)
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/*
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* cache_tx39_op_32lines_16:
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*
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* Perform the specified cache operation on 32 16-byte
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* cache lines.
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*/
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#define cache_tx39_op_32lines_16(va, op) \
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do { \
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__asm __volatile( \
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".set noreorder \n\t" \
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".set push \n\t" \
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".set mips3 \n\t" \
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"cache %1, 0x000(%0); cache %1, 0x010(%0); \n\t" \
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"cache %1, 0x020(%0); cache %1, 0x030(%0); \n\t" \
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"cache %1, 0x040(%0); cache %1, 0x050(%0); \n\t" \
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"cache %1, 0x060(%0); cache %1, 0x070(%0); \n\t" \
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"cache %1, 0x080(%0); cache %1, 0x090(%0); \n\t" \
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"cache %1, 0x0a0(%0); cache %1, 0x0b0(%0); \n\t" \
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"cache %1, 0x0c0(%0); cache %1, 0x0d0(%0); \n\t" \
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"cache %1, 0x0e0(%0); cache %1, 0x0f0(%0); \n\t" \
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"cache %1, 0x100(%0); cache %1, 0x110(%0); \n\t" \
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"cache %1, 0x120(%0); cache %1, 0x130(%0); \n\t" \
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"cache %1, 0x140(%0); cache %1, 0x150(%0); \n\t" \
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"cache %1, 0x160(%0); cache %1, 0x170(%0); \n\t" \
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"cache %1, 0x180(%0); cache %1, 0x190(%0); \n\t" \
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"cache %1, 0x1a0(%0); cache %1, 0x1b0(%0); \n\t" \
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"cache %1, 0x1c0(%0); cache %1, 0x1d0(%0); \n\t" \
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"cache %1, 0x1e0(%0); cache %1, 0x1f0(%0); \n\t" \
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".set pop \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory"); \
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} while (/*CONSTCOND*/0)
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void tx3900_icache_sync_all_16(void);
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void tx3900_icache_sync_range_16(vaddr_t, vsize_t);
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void tx3900_pdcache_wbinv_all_4(void);
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void tx3900_pdcache_inv_range_4(vaddr_t, vsize_t);
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void tx3900_pdcache_wb_range_4(vaddr_t, vsize_t);
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void tx3920_icache_sync_all_16wb(void);
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void tx3920_icache_sync_range_16wt(vaddr_t, vsize_t);
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void tx3920_icache_sync_range_16wb(vaddr_t, vsize_t);
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void tx3920_pdcache_wbinv_all_16wt(void);
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void tx3920_pdcache_wbinv_all_16wb(void);
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void tx3920_pdcache_wbinv_range_16wb(vaddr_t, vsize_t);
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void tx3920_pdcache_inv_range_16(vaddr_t, vsize_t);
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void tx3920_pdcache_wb_range_16wt(vaddr_t, vsize_t);
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void tx3920_pdcache_wb_range_16wb(vaddr_t, vsize_t);
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void tx3900_icache_do_inv_index_16(vaddr_t, vsize_t);
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void tx3920_icache_do_inv_16(vaddr_t, vsize_t);
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#endif /* !_LOCORE */
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