360 lines
9.3 KiB
C
360 lines
9.3 KiB
C
/* $NetBSD: piix.c,v 1.8 2004/05/01 06:35:10 kochi Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Support for the Intel PIIX PCI-ISA bridge interrupt controller
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* and ICHn I/O controller hub
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*/
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/*
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* ICH2 and later support 8 interrupt routers while the first
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* generation (ICH and ICH0) support 4 which is same as PIIX.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: piix.c,v 1.8 2004/05/01 06:35:10 kochi Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <machine/intr.h>
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#include <machine/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <i386/pci/pci_intr_fixup.h>
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#include <i386/pci/piixreg.h>
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#include <i386/pci/piixvar.h>
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#ifdef PIIX_DEBUG
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#define DPRINTF(arg) printf arg
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#else
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#define DPRINTF(arg)
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#endif
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int piix_getclink(pciintr_icu_handle_t, int, int *);
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int ich_getclink(pciintr_icu_handle_t, int, int *);
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int piix_get_intr(pciintr_icu_handle_t, int, int *);
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int piix_set_intr(pciintr_icu_handle_t, int, int);
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#ifdef PIIX_DEBUG
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void piix_pir_dump(struct piix_handle *);
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void ich_pir_dump(struct piix_handle *);
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#endif
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const struct pciintr_icu piix_pci_icu = {
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piix_getclink,
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piix_get_intr,
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piix_set_intr,
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piix_get_trigger,
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piix_set_trigger,
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};
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const struct pciintr_icu ich_pci_icu = {
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ich_getclink,
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piix_get_intr,
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piix_set_intr,
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piix_get_trigger,
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piix_set_trigger,
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};
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static int piix_max_link = 3;
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int
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piix_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag,
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pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp)
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{
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struct piix_handle *ph;
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ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT);
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if (ph == NULL)
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return (1);
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ph->ph_iot = iot;
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ph->ph_pc = pc;
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ph->ph_tag = tag;
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if (bus_space_map(iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0,
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&ph->ph_elcr_ioh) != 0) {
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free(ph, M_DEVBUF);
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return (1);
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}
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#ifdef PIIX_DEBUG
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piix_pir_dump(ph);
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#endif
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*ptagp = &piix_pci_icu;
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*phandp = ph;
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return (0);
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}
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int
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ich_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag,
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pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp)
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{
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int rv;
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rv = piix_init(pc, iot, tag, ptagp, phandp);
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if (rv == 0) {
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piix_max_link = 7;
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*ptagp = &ich_pci_icu;
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#ifdef PIIX_DEBUG
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ich_pir_dump(*phandp);
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#endif
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}
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return (rv);
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}
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int
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piix_getclink(pciintr_icu_handle_t v, int link, int *clinkp)
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{
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DPRINTF(("PIIX link value 0x%x: ", link));
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/* Pattern 1: simple. */
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if (PIIX_LEGAL_LINK(link - 1)) {
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*clinkp = link - 1;
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DPRINTF(("PIRQ %d (simple)\n", *clinkp));
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return (0);
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}
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/* Pattern 2: configuration register offset */
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if (link >= 0x60 && link <= 0x63) {
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*clinkp = link - 0x60;
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DPRINTF(("PIRQ %d (register offset)\n", *clinkp));
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return (0);
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}
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/*
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* XXX Pattern 3: configuration register offset 1
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* Some BIOS return 0x68, 0x69
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*/
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if (link >= 0x68 && link <= 0x69) {
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*clinkp = link - 0x67;
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DPRINTF(("PIRQ %d (register offset 1)\n", *clinkp));
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return (0);
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}
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DPRINTF(("bogus IRQ selection source\n"));
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return (1);
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}
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int
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ich_getclink(pciintr_icu_handle_t v, int link, int *clinkp)
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{
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/*
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* configuration registers 0x68..0x6b are for PIRQ[EFGH]
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*/
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if (link >= 0x68 && link <= 0x6b) {
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*clinkp = link - 0x68 + 4;
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DPRINTF(("PIIX link value 0x%x: ", link));
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DPRINTF(("PIRQ %d (register offset)\n", *clinkp));
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return (0);
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}
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return piix_getclink(v, link, clinkp);
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}
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int
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piix_get_intr(pciintr_icu_handle_t v, int clink, int *irqp)
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{
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struct piix_handle *ph = v;
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int shift;
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pcireg_t reg;
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int cfgreg;
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if (PIIX_LEGAL_LINK(clink) == 0)
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return (1);
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cfgreg = clink <= 3 ? PIIX_CFG_PIRQ : PIIX_CFG_PIRQ2;
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clink &= 0x03;
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reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg);
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shift = clink << 3;
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if ((reg >> shift) & PIIX_CFG_PIRQ_NONE)
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*irqp = X86_PCI_INTERRUPT_LINE_NO_CONNECTION;
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else
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*irqp = PIIX_PIRQ(reg, clink);
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return (0);
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}
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int
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piix_set_intr(pciintr_icu_handle_t v, int clink, int irq)
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{
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struct piix_handle *ph = v;
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int shift;
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pcireg_t reg;
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int cfgreg;
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if (PIIX_LEGAL_LINK(clink) == 0 || PIIX_LEGAL_IRQ(irq) == 0)
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return (1);
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cfgreg = clink <= 3 ? PIIX_CFG_PIRQ : PIIX_CFG_PIRQ2;
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clink &= 0x03;
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reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg);
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shift = clink << 3;
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reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift);
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reg |= irq << shift;
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pci_conf_write(ph->ph_pc, ph->ph_tag, cfgreg, reg);
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return (0);
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}
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int
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piix_get_trigger(pciintr_icu_handle_t v, int irq, int *triggerp)
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{
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struct piix_handle *ph = v;
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int off, bit;
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u_int8_t elcr;
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if (PIIX_LEGAL_IRQ(irq) == 0)
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return (1);
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off = (irq > 7) ? 1 : 0;
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bit = irq & 7;
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elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off);
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if (elcr & (1 << bit))
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*triggerp = IST_LEVEL;
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else
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*triggerp = IST_EDGE;
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return (0);
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}
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int
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piix_set_trigger(pciintr_icu_handle_t v, int irq, int trigger)
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{
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struct piix_handle *ph = v;
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int off, bit;
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u_int8_t elcr;
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if (PIIX_LEGAL_IRQ(irq) == 0)
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return (1);
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off = (irq > 7) ? 1 : 0;
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bit = irq & 7;
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elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off);
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if (trigger == IST_LEVEL)
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elcr |= (1 << bit);
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else
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elcr &= ~(1 << bit);
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bus_space_write_1(ph->ph_iot, ph->ph_elcr_ioh, off, elcr);
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return (0);
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}
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#ifdef PIIX_DEBUG
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void
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piix_pir_dump(struct piix_handle *ph)
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{
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int i, irq;
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pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ);
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u_int8_t elcr[2];
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elcr[0] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 0);
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elcr[1] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 1);
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for (i = 0; i < 4; i++) {
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irq = PIIX_PIRQ(irqs, i);
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if (irq & PIIX_CFG_PIRQ_NONE)
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printf("PIIX PIRQ %d: irq none (0x%x)\n", i, irq);
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else
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printf("PIIX PIRQ %d: irq %d\n", i, irq);
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}
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printf("PIIX irq:");
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for (i = 0; i < 16; i++)
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printf(" %2d", i);
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printf("\n");
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printf(" trigger:");
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for (i = 0; i < 16; i++)
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printf(" %c", (elcr[(i & 8) ? 1 : 0] & (1 << (i & 7))) ?
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'L' : 'E');
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printf("\n");
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}
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void
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ich_pir_dump(struct piix_handle *ph)
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{
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int i, irq;
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pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ2);
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for (i = 0; i < 4; i++) {
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irq = PIIX_PIRQ(irqs, i);
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if (irq & PIIX_CFG_PIRQ_NONE)
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printf("PIIX PIRQ %d: irq none (0x%x)\n", i+4, irq);
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else
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printf("PIIX PIRQ %d: irq %d\n", i+4, irq);
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}
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}
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#endif /* PIIX_DEBUG */
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