d85a75f583
is the historical name for this interrupt level, and the historical name is going to go away in the near future).
150 lines
5.1 KiB
C
150 lines
5.1 KiB
C
/* $NetBSD: intr.h,v 1.8 2001/01/14 02:00:40 thorpej Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Jonathan Stone for
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* the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HPCMIPS_INTR_H_
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#define _HPCMIPS_INTR_H_
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#define IPL_NONE 0 /* disable only this interrupt */
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#define IPL_BIO 1 /* disable block I/O interrupts */
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#define IPL_NET 2 /* disable network interrupts */
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#define IPL_TTY 3 /* disable terminal interrupts */
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#define IPL_CLOCK 4 /* disable clock interrupts */
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#define IPL_STATCLOCK 5 /* disable profiling interrupts */
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#if 0 /* XXX */
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#define IPL_SERIAL 6 /* disable serial hardware interrupts */
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#endif
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#define IPL_DMA 7 /* disable DMA reload interrupts */
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#define IPL_HIGH 8 /* disable all interrupts */
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#ifdef _KERNEL
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#ifndef _LOCORE
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#include <mips/cpuregs.h>
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int _splraise __P((int));
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int _spllower __P((int));
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int _splset __P((int));
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int _splget __P((void));
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void _splnone __P((void));
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void _setsoftintr __P((int));
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void _clrsoftintr __P((int));
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#define splhigh() _splraise(MIPS_INT_MASK)
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#define spl0() (void)_spllower(0)
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#define splx(s) (void)_splset(s)
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#define splbio() (_splraise(splvec.splbio))
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#define splnet() (_splraise(splvec.splnet))
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#define spltty() (_splraise(splvec.spltty))
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#define splimp() (_splraise(splvec.splimp))
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#define splvm() (_splraise(splvec.splimp))
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#define splclock() (_splraise(splvec.splclock))
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#define splstatclock() (_splraise(splvec.splstatclock))
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#define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0)
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#define splsoftclock() _splraise(MIPS_SOFT_INT_MASK_0)
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#define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
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#define splsched() splhigh()
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#define spllock() splhigh()
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struct splvec {
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int splbio;
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int splnet;
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int spltty;
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int splimp;
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int splclock;
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int splstatclock;
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};
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extern struct splvec splvec;
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/* Conventionals ... */
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#define MIPS_SPLHIGH (MIPS_INT_MASK)
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#define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
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#define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
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#define MIPS_SPL2 (MIPS_INT_MASK_2|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
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#define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
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#define MIPS_SPL4 (MIPS_INT_MASK_4|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
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#define MIPS_SPL_0_1 (MIPS_INT_MASK_1|MIPS_SPL0)
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#define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1)
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#define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1)
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#define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2)
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#define MIPS_SPL_2_4 (MIPS_INT_MASK_4|MIPS_SPL2)
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/*
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* Index into intrcnt[], which is defined in locore
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*/
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extern u_long intrcnt[];
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#define SOFTCLOCK_INTR 0
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#define SOFTNET_INTR 1
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#define SERIAL0_INTR 2
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#define SERIAL1_INTR 3
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#define SERIAL2_INTR 4
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#define LANCE_INTR 5
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#define SCSI_INTR 6
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#define ERROR_INTR 7
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#define HARDCLOCK 8
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#define FPU_INTR 9
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#define SLOT0_INTR 10
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#define SLOT1_INTR 11
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#define SLOT2_INTR 12
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#define DTOP_INTR 13
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#define ISDN_INTR 14
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#define FLOPPY_INTR 15
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#define STRAY_INTR 16
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/*
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* software simulated interrupt
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*/
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extern unsigned ssir;
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#define SIR_NET 0x1
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#define setsoftnet() setsoft(SIR_NET)
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#define setsoft(x) \
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do { ssir |= (x); _setsoftintr(MIPS_SOFT_INT_MASK_1); } while (0)
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#define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0)
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#define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0)
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#define clearsoftnet() _clrsoftintr(MIPS_SOFT_INT_MASK_1)
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#endif /* !_LOCORE */
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#endif /* _KERNEL */
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#endif /* !_HPCMIPS_INTR_H_ */
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