559 lines
14 KiB
C
559 lines
14 KiB
C
/* $NetBSD: rgephy.c,v 1.7 2005/12/11 12:22:42 christos Exp $ */
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/*
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* Copyright (c) 2003
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.7 2005/12/11 12:22:42 christos Exp $");
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/*
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* Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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#include <dev/mii/rgephyreg.h>
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#include <dev/ic/rtl81x9reg.h>
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static int rgephy_match(struct device *, struct cfdata *, void *);
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static void rgephy_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(rgephy, sizeof(struct mii_softc),
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rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate);
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static int rgephy_service(struct mii_softc *, struct mii_data *, int);
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static void rgephy_status(struct mii_softc *);
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static int rgephy_mii_phy_auto(struct mii_softc *);
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static void rgephy_reset(struct mii_softc *);
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static void rgephy_loop(struct mii_softc *);
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static void rgephy_load_dspcode(struct mii_softc *);
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static int rgephy_mii_model;
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static const struct mii_phy_funcs rgephy_funcs = {
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rgephy_service, rgephy_status, rgephy_reset,
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};
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static const struct mii_phydesc rgephys[] = {
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{ MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S,
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MII_STR_xxREALTEK_RTL8169S },
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{ MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S,
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MII_STR_REALTEK_RTL8169S },
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{ 0, 0,
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NULL }
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};
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static int
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rgephy_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct mii_attach_args *ma = aux;
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if (mii_phy_match(ma, rgephys) != NULL)
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return (10);
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return (0);
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}
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static void
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rgephy_attach(struct device *parent, struct device *self, void *aux)
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{
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struct mii_softc *sc = (struct mii_softc *)self;
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struct mii_attach_args *ma = aux;
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struct mii_data *mii = ma->mii_data;
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const struct mii_phydesc *mpd;
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int rev;
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const char *sep = "";
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rev = MII_REV(ma->mii_id2);
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mpd = mii_phy_match(ma, rgephys);
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aprint_naive(": Media interface\n");
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aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev);
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sc->mii_mpd_model = rev; /* XXX miivar.h comment vs usage? */
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_pdata = mii;
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sc->mii_flags = mii->mii_flags;
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sc->mii_anegticks = 5;
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sc->mii_funcs = &rgephy_funcs;
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/* Don't do isolate on this PHY. */
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sc->mii_flags |= MIIF_NOISOLATE;
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#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
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#define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", "
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#if 0
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
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BMCR_ISO);
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#endif
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#ifdef __FreeBSD__
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
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BMCR_LOOP|BMCR_S100);
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#endif
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rgephy_mii_model = MII_MODEL(ma->mii_id2);
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PHY_RESET(sc);
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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sc->mii_capabilities &= ~BMSR_ANEG;
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/*
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* FreeBSD does not check EXSTAT, but instead adds gigabit
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* media explicitly. Why?
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*/
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aprint_normal("%s: ", sc->mii_dev.dv_xname);
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#ifdef __FreeBSD__
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mii_phy_add_media(sc);
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
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RGEPHY_BMCR_FDX);
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PRINT(", 1000baseTX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0);
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PRINT("1000baseTX-FDX");
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#else
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if (sc->mii_capabilities & BMSR_EXTSTAT) {
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sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
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}
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mii_phy_add_media(sc);
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#endif
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/* rtl8169S does not report auto-sense; add manually. */
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA);
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sep =", ";
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PRINT("auto");
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#undef ADD
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#undef PRINT
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aprint_normal("\n");
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}
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static int
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rgephy_service(sc, mii, cmd)
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struct mii_softc *sc;
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struct mii_data *mii;
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int cmd;
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int reg, speed, gig;
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switch (cmd) {
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case MII_POLLSTAT:
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/*
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* If we're not polling our PHY instance, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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reg = PHY_READ(sc, MII_BMCR);
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PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
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return (0);
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}
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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PHY_RESET(sc); /* XXX hardware bug work-around */
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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#ifdef foo
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/*
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* If we're already in auto mode, just return.
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*/
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if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
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return (0);
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#endif
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(void) rgephy_mii_phy_auto(sc);
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break;
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case IFM_1000_T:
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speed = RGEPHY_S1000;
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goto setit;
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case IFM_100_TX:
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speed = RGEPHY_S100;
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goto setit;
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case IFM_10_T:
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speed = RGEPHY_S10;
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setit:
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rgephy_loop(sc);
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
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speed |= RGEPHY_BMCR_FDX;
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gig = RGEPHY_1000CTL_AFD;
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} else {
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gig = RGEPHY_1000CTL_AHD;
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}
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PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
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PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
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PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
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break;
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PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
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PHY_WRITE(sc, RGEPHY_MII_BMCR,
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speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
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/*
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* When settning the link manually, one side must
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* be the master and the other the slave. However
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* ifmedia doesn't give us a good way to specify
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* this, so we fake it by using one of the LINK
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* flags. If LINK0 is set, we program the PHY to
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* be a master, otherwise it's a slave.
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*/
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if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
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PHY_WRITE(sc, RGEPHY_MII_1000CTL,
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gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
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} else {
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PHY_WRITE(sc, RGEPHY_MII_1000CTL,
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gig|RGEPHY_1000CTL_MSE);
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}
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break;
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#ifdef foo
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case IFM_NONE:
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PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
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break;
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#endif
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case IFM_100_T4:
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default:
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return (EINVAL);
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}
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break;
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case MII_TICK:
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/*
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* If we're not currently selected, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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/*
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* Is the interface even up?
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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/*
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* Only used for autonegotiation.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
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break;
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/*
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* Check to see if we have link. If we do, we don't
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* need to restart the autonegotiation process. Read
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* the BMSR twice in case it's latched.
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*/
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reg = PHY_READ(sc, RTK_GMEDIASTAT);
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if (reg & RTK_GMEDIASTAT_LINK)
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break;
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/*
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* Only retry autonegotiation every 5 seconds.
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*/
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if (++sc->mii_ticks <= 5/*10*/)
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break;
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sc->mii_ticks = 0;
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rgephy_mii_phy_auto(sc);
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return (0);
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}
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/* Update the media status. */
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rgephy_status(sc);
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/*
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* Callback if something changed. Note that we need to poke
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* the DSP on the RealTek PHYs if the media changes.
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*
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*/
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if (sc->mii_media_active != mii->mii_media_active ||
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sc->mii_media_status != mii->mii_media_status ||
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cmd == MII_MEDIACHG) {
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/* XXX only for v0/v1 phys. */
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if (sc->mii_mpd_model < 2)
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rgephy_load_dspcode(sc);
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}
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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rgephy_status(sc)
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struct mii_softc *sc;
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{
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struct mii_data *mii = sc->mii_pdata;
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int bmsr, bmcr;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, RTK_GMEDIASTAT);
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if (bmsr & RTK_GMEDIASTAT_LINK)
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mii->mii_media_status |= IFM_ACTIVE;
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bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
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bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
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if (bmcr & RGEPHY_BMCR_ISO) {
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mii->mii_media_active |= IFM_NONE;
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mii->mii_media_status = 0;
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return;
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}
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if (bmcr & RGEPHY_BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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if (bmcr & RGEPHY_BMCR_AUTOEN) {
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if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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}
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bmsr = PHY_READ(sc, RTK_GMEDIASTAT);
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if (bmsr & RTK_GMEDIASTAT_10MBPS)
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mii->mii_media_active |= IFM_10_T;
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if (bmsr & RTK_GMEDIASTAT_100MBPS)
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mii->mii_media_active |= IFM_100_TX;
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if (bmsr & RTK_GMEDIASTAT_1000MBPS)
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mii->mii_media_active |= IFM_1000_T;
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if (bmsr & RTK_GMEDIASTAT_FDX)
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mii->mii_media_active |= IFM_FDX;
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return;
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}
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static int
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rgephy_mii_phy_auto(mii)
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struct mii_softc *mii;
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{
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rgephy_loop(mii);
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PHY_RESET(mii);
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PHY_WRITE(mii, RGEPHY_MII_ANAR,
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BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
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DELAY(1000);
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PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD);
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DELAY(1000);
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PHY_WRITE(mii, RGEPHY_MII_BMCR,
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RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
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DELAY(100);
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return (EJUSTRETURN);
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}
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static void
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rgephy_loop(struct mii_softc *sc)
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{
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u_int32_t bmsr;
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int i;
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PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
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DELAY(1000);
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for (i = 0; i < 15000; i++) {
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bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
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if (!(bmsr & RGEPHY_BMSR_LINK)) {
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#if 0
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device_printf(sc->mii_dev, "looped %d\n", i);
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#endif
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break;
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}
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DELAY(10);
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}
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}
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#define PHY_SETBIT(x, y, z) \
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PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
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#define PHY_CLRBIT(x, y, z) \
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PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
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/*
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* Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
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* existing revisions of the 8169S/8110S chips need to be tuned in
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* order to reliably negotiate a 1000Mbps link. Later revs of the
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* chips may not require this software tuning.
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*/
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static void
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rgephy_load_dspcode(struct mii_softc *sc)
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{
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int val;
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#if 1
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PHY_WRITE(sc, 31, 0x0001);
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PHY_WRITE(sc, 21, 0x1000);
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PHY_WRITE(sc, 24, 0x65C7);
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PHY_CLRBIT(sc, 4, 0x0800);
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val = PHY_READ(sc, 4) & 0xFFF;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0x00A1);
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PHY_WRITE(sc, 2, 0x0008);
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PHY_WRITE(sc, 1, 0x1020);
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PHY_WRITE(sc, 0, 0x1000);
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PHY_SETBIT(sc, 4, 0x0800);
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PHY_CLRBIT(sc, 4, 0x0800);
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val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0xFF41);
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PHY_WRITE(sc, 2, 0xDE60);
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PHY_WRITE(sc, 1, 0x0140);
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PHY_WRITE(sc, 0, 0x0077);
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val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0xDF01);
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PHY_WRITE(sc, 2, 0xDF20);
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PHY_WRITE(sc, 1, 0xFF95);
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PHY_WRITE(sc, 0, 0xFA00);
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val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0xFF41);
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PHY_WRITE(sc, 2, 0xDE20);
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PHY_WRITE(sc, 1, 0x0140);
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PHY_WRITE(sc, 0, 0x00BB);
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val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0xDF01);
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PHY_WRITE(sc, 2, 0xDF20);
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|
PHY_WRITE(sc, 1, 0xFF95);
|
|
PHY_WRITE(sc, 0, 0xBF00);
|
|
PHY_SETBIT(sc, 4, 0x0800);
|
|
PHY_CLRBIT(sc, 4, 0x0800);
|
|
PHY_WRITE(sc, 31, 0x0000);
|
|
#else
|
|
(void)val;
|
|
PHY_WRITE(sc, 0x1f, 0x0001);
|
|
PHY_WRITE(sc, 0x15, 0x1000);
|
|
PHY_WRITE(sc, 0x18, 0x65c7);
|
|
PHY_WRITE(sc, 0x04, 0x0000);
|
|
PHY_WRITE(sc, 0x03, 0x00a1);
|
|
PHY_WRITE(sc, 0x02, 0x0008);
|
|
PHY_WRITE(sc, 0x01, 0x1020);
|
|
PHY_WRITE(sc, 0x00, 0x1000);
|
|
PHY_WRITE(sc, 0x04, 0x0800);
|
|
PHY_WRITE(sc, 0x04, 0x0000);
|
|
PHY_WRITE(sc, 0x04, 0x7000);
|
|
PHY_WRITE(sc, 0x03, 0xff41);
|
|
PHY_WRITE(sc, 0x02, 0xde60);
|
|
PHY_WRITE(sc, 0x01, 0x0140);
|
|
PHY_WRITE(sc, 0x00, 0x0077);
|
|
PHY_WRITE(sc, 0x04, 0x7800);
|
|
PHY_WRITE(sc, 0x04, 0x7000);
|
|
PHY_WRITE(sc, 0x04, 0xa000);
|
|
PHY_WRITE(sc, 0x03, 0xdf01);
|
|
PHY_WRITE(sc, 0x02, 0xdf20);
|
|
PHY_WRITE(sc, 0x01, 0xff95);
|
|
PHY_WRITE(sc, 0x00, 0xfa00);
|
|
PHY_WRITE(sc, 0x04, 0xa800);
|
|
PHY_WRITE(sc, 0x04, 0xa000);
|
|
PHY_WRITE(sc, 0x04, 0xb000);
|
|
PHY_WRITE(sc, 0x0e, 0xff41);
|
|
PHY_WRITE(sc, 0x02, 0xde20);
|
|
PHY_WRITE(sc, 0x01, 0x0140);
|
|
PHY_WRITE(sc, 0x00, 0x00bb);
|
|
PHY_WRITE(sc, 0x04, 0xb800);
|
|
PHY_WRITE(sc, 0x04, 0xb000);
|
|
PHY_WRITE(sc, 0x04, 0xf000);
|
|
PHY_WRITE(sc, 0x03, 0xdf01);
|
|
PHY_WRITE(sc, 0x02, 0xdf20);
|
|
PHY_WRITE(sc, 0x01, 0xff95);
|
|
PHY_WRITE(sc, 0x00, 0xbf00);
|
|
PHY_WRITE(sc, 0x04, 0xf800);
|
|
PHY_WRITE(sc, 0x04, 0xf000);
|
|
PHY_WRITE(sc, 0x04, 0x0000);
|
|
PHY_WRITE(sc, 0x1f, 0x0000);
|
|
PHY_WRITE(sc, 0x0b, 0x0000);
|
|
|
|
#endif
|
|
|
|
DELAY(40);
|
|
}
|
|
|
|
static void
|
|
rgephy_reset(struct mii_softc *sc)
|
|
{
|
|
mii_phy_reset(sc);
|
|
DELAY(1000);
|
|
|
|
if (sc->mii_mpd_model < 2)
|
|
rgephy_load_dspcode(sc);
|
|
else {
|
|
PHY_WRITE(sc, 0x1F, 0x0001);
|
|
PHY_WRITE(sc, 0x09, 0x273a);
|
|
PHY_WRITE(sc, 0x0e, 0x7bfb);
|
|
PHY_WRITE(sc, 0x1b, 0x841e);
|
|
|
|
PHY_WRITE(sc, 0x1F, 0x0002);
|
|
PHY_WRITE(sc, 0x01, 0x90D0);
|
|
PHY_WRITE(sc, 0x1F, 0x0000);
|
|
}
|
|
|
|
/* Reset capabilities */
|
|
/* Step1: write our capability */
|
|
PHY_WRITE(sc, 0x04,0x01e1); /* 10/100 capability */
|
|
PHY_WRITE(sc, 0x09,0x0200); /* 1000 capability */
|
|
|
|
#ifdef jrs_notyet
|
|
/* Step2: Restart NWay */
|
|
PHY_WRITE(sc, 0x00, 0x1200); // NWay enable and Restart NWay
|
|
#endif
|
|
}
|