525 lines
17 KiB
C
525 lines
17 KiB
C
/**************************************************************************
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**
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** $Id: ncr_reg.h,v 1.1 1994/08/09 22:20:49 mycroft Exp $
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**
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** Device driver for the NCR 53C810 PCI-SCSI-Controller.
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**
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** 386bsd / FreeBSD / NetBSD
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**
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**-------------------------------------------------------------------------
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**
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** Written for 386bsd and FreeBSD by
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** wolf@dentaro.gun.de Wolfgang Stanglmeier
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** se@mi.Uni-Koeln.de Stefan Esser
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**
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** Ported to NetBSD by
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** mycroft@gnu.ai.mit.edu
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**
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**-------------------------------------------------------------------------
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**
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** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without
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** modification, are permitted provided that the following conditions
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** are met:
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** 1. Redistributions of source code must retain the above copyright
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** notice, this list of conditions and the following disclaimer.
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** 2. Redistributions in binary form must reproduce the above copyright
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** notice, this list of conditions and the following disclaimer in the
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** documentation and/or other materials provided with the distribution.
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** 3. The name of the author may not be used to endorse or promote products
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** derived from this software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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**-------------------------------------------------------------------------
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**
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** $Log: ncr_reg.h,v $
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** Revision 1.1 1994/08/09 22:20:49 mycroft
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** Add NCR 53c8XX driver, originally from Wolfgang Stanglmeier.
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**
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** Revision 2.0.0.4 94/08/09 23:10:10 wolf
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** new message.
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**
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** Revision 2.0.0.3 94/07/24 08:59:19 wolf
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** bits of sstat0 defined.
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**
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** Revision 2.0 94/07/10 15:53:27 wolf
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** FreeBSD release.
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**
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** Revision 1.0 94/06/07 20:02:21 wolf
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** Beta release.
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**
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***************************************************************************
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*/
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#ifndef __NCR_REG_H__
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#define __NCR_REG_H__
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/*-----------------------------------------------------------------
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**
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** The ncr 53c810 register structure.
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**
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**-----------------------------------------------------------------
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*/
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struct ncr_reg {
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/*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
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/*01*/ u_char nc_scntl1; /* no reset */
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#define ISCON 0x10 /* connected to scsi */
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#define CRST 0x08 /* force reset */
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/*02*/ u_char nc_scntl2; /* no disconnect expected */
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/*03*/ u_char nc_scntl3; /* cnf system clock dependent */
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/*04*/ u_char nc_scid; /* cnf host adapter scsi address */
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#define RRE 0x40 /* r/w:e enable response to resel. */
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#define SRE 0x20 /* r/w:e enable response to select */
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/*05*/ u_char nc_sxfer; /* ### Sync speed and count */
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/*06*/ u_char nc_sdid; /* ### Destination-ID */
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/*07*/ u_char nc_gpreg; /* ??? IO-Pins */
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/*08*/ u_char nc_sfbr; /* ### First byte in phase */
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/*09*/ u_char nc_socl;
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#define CREQ 0x80 /* r/w: SCSI-REQ */
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#define CACK 0x40 /* r/w: SCSI-ACK */
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#define CBSY 0x20 /* r/w: SCSI-BSY */
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#define CSEL 0x10 /* r/w: SCSI-SEL */
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#define CATN 0x08 /* r/w: SCSI-ATN */
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#define CMSG 0x04 /* r/w: SCSI-MSG */
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#define CC_D 0x02 /* r/w: SCSI-C_D */
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#define CI_O 0x01 /* r/w: SCSI-I_O */
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/*0a*/ u_char nc_ssid;
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/*0b*/ u_char nc_sbcl;
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/*0c*/ u_char nc_dstat;
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#define DFE 0x80 /* sta: dma fifo empty */
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#define MDPE 0x40 /* int: master data parity error */
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#define BF 0x20 /* int: script: bus fault */
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#define ABRT 0x10 /* int: script: command aborted */
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#define SSI 0x08 /* int: script: single step */
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#define SIR 0x04 /* int: script: interrupt instruct. */
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#define IID 0x01 /* int: script: illegal instruct. */
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/*0d*/ u_char nc_sstat0;
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#define ILF 0x80 /* sta: data in SIDL register */
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#define ORF 0x40 /* sta: data in SODR register */
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#define OLF 0x20 /* sta: data in SODL register */
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#define AIP 0x10 /* sta: arbitration in progress */
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#define LOA 0x08 /* sta: arbitration lost */
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#define WOA 0x04 /* sta: arbitration won */
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#define IRST 0x02 /* sta: scsi reset signal */
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#define SDP 0x01 /* sta: scsi parity signal */
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/*0e*/ u_char nc_sstat1;
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/*0f*/ u_char nc_sstat2;
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/*10*/ u_long nc_dsa; /* --> Base page */
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/*14*/ u_char nc_istat; /* --> Main Command and status */
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#define CABRT 0x80 /* cmd: abort current operation */
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#define SRST 0x40 /* mod: reset chip */
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#define SIGP 0x20 /* r/w: message from host to ncr */
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#define SEM 0x10 /* r/w: message between host + ncr */
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#define CON 0x08 /* sta: connected to scsi */
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#define INTF 0x04 /* sta: int on the fly (reset by wr)*/
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#define SIP 0x02 /* sta: scsi-interupt */
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#define DIP 0x01 /* sta: host/script interupt */
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/*15*/ u_char nc_15_;
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/*16*/ u_char nc_16_;
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/*17*/ u_char nc_17_;
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/*18*/ u_char nc_ctest0;
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/*19*/ u_char nc_ctest1;
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/*1a*/ u_char nc_ctest2;
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#define CSIGP 0x40
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/*1b*/ u_char nc_ctest3;
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#define CLF 0x04 /* clear scsi fifo */
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/*1c*/ u_long nc_temp; /* ### Temporary stack */
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/*20*/ u_char nc_dfifo;
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/*21*/ u_char nc_ctest4;
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/*22*/ u_char nc_ctest5;
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/*23*/ u_char nc_ctest6;
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/*24*/ u_long nc_dbc; /* ### Byte count and command */
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/*28*/ u_long nc_dnad; /* ### Next command register */
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/*2c*/ u_long nc_dsp; /* --> Script Pointer */
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/*30*/ u_long nc_dsps; /* --> Script pointer save/opcode#2 */
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/*34*/ u_long nc_scratcha; /* ??? Temporary register a */
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/*38*/ u_char nc_dmode;
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/*39*/ u_char nc_dien;
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/*3a*/ u_char nc_dwt;
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/*3b*/ u_char nc_dcntl; /* --> Script execution control */
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#define SSM 0x10 /* mod: single step mode */
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#define STD 0x04 /* cmd: start dma mode */
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#define NOCOM 0x01 /* cmd: protect sfbr while reselect */
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/*3c*/ u_long nc_adder;
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/*40*/ u_short nc_sien; /* -->: interupt enable */
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/*42*/ u_short nc_sist; /* <--: interupt status */
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#define STO 0x0400/* sta: timeout (select) */
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#define GEN 0x0200/* sta: timeout (general) */
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#define HTH 0x0100/* sta: timeout (handshake) */
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#define MA 0x80 /* sta: phase mismatch */
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#define CMP 0x40 /* sta: arbitration complete */
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#define SEL 0x20 /* sta: selected by another device */
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#define RSL 0x10 /* sta: reselected by another device*/
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#define SGE 0x08 /* sta: gross error (over/underflow)*/
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#define UDC 0x04 /* sta: unexpected disconnect */
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#define RST 0x02 /* sta: scsi bus reset detected */
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#define PAR 0x01 /* sta: scsi parity error */
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/*44*/ u_char nc_slpar;
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/*45*/ u_char nc_45_;
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/*46*/ u_char nc_macntl;
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/*47*/ u_char nc_gpcntl;
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/*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
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/*49*/ u_char nc_stime1; /* cmd: timeout user defined */
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/*4a*/ u_char nc_respid; /* sta: Reselect-IDs */
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/*4b*/ u_char nc_4b_;
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/*4c*/ u_char nc_stest0;
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/*4d*/ u_char nc_stest1;
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/*4e*/ u_char nc_stest2;
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#define ROF 0x40 /* reset scsi offset (after gross error!) */
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#define EXT 0x02 /* extended filtering */
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/*4f*/ u_char nc_stest3;
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#define TE 0x80 /* c: tolerAnt enable */
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#define CSF 0x02 /* c: clear scsi fifo */
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/*50*/ u_char nc_sidl; /* Lowlevel: latched from scsi data */
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/*51*/ u_char nc_51_;
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/*52*/ u_char nc_52_;
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/*53*/ u_char nc_53_;
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/*54*/ u_char nc_sodl; /* Lowlevel: data out to scsi data */
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/*55*/ u_char nc_55_;
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/*56*/ u_char nc_56_;
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/*57*/ u_char nc_57_;
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/*58*/ u_char nc_sbdl; /* Lowlevel: data from scsi data */
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/*59*/ u_char nc_59_;
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/*5a*/ u_char nc_5a_;
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/*5b*/ u_char nc_5b_;
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/*5c*/ u_char nc_scr0; /* Working register B */
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/*5d*/ u_char nc_scr1; /* */
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/*5e*/ u_char nc_scr2; /* */
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/*5f*/ u_char nc_scr3; /* */
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/*60*/
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};
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/*-----------------------------------------------------------
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**
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** Utility macros for the script.
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**
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**-----------------------------------------------------------
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*/
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#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
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#define REG(r) REGJ (nc_, r)
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#ifndef TARGET_MODE
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#define TARGET_MODE 0
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#endif
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typedef unsigned long ncrcmd;
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/*-----------------------------------------------------------
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**
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** SCSI phases
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**
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**-----------------------------------------------------------
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*/
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#define SCR_DATA_OUT 0x00000000
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#define SCR_DATA_IN 0x01000000
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#define SCR_COMMAND 0x02000000
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#define SCR_STATUS 0x03000000
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#define SCR_ILG_OUT 0x04000000
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#define SCR_ILG_IN 0x05000000
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#define SCR_MSG_OUT 0x06000000
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#define SCR_MSG_IN 0x07000000
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/*-----------------------------------------------------------
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**
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** Data transfer via SCSI.
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**
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**-----------------------------------------------------------
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**
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** MOVE_ABS (LEN)
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** <<start address>>
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**
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** MOVE_IND (LEN)
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** <<dnad_offset>>
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**
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** MOVE_TBL
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** <<dnad_offset>>
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**
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**-----------------------------------------------------------
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*/
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#define SCR_MOVE_ABS(l) ((0x08000000 ^ (TARGET_MODE << 1ul)) | (l))
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#define SCR_MOVE_IND(l) ((0x28000000 ^ (TARGET_MODE << 1ul)) | (l))
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#define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul))
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struct scr_tblmove {
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u_long size;
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u_long addr;
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};
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/*-----------------------------------------------------------
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**
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** Selection
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**
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**-----------------------------------------------------------
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**
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** SEL_ABS | SCR_ID (0..7) [ | REL_JMP]
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** <<alternate_address>>
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**
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** SEL_TBL | << dnad_offset>> [ | REL_JMP]
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** <<alternate_address>>
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**
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**-----------------------------------------------------------
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*/
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#define SCR_SEL_ABS 0x40000000
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#define SCR_SEL_ABS_ATN 0x41000000
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#define SCR_SEL_TBL 0x42000000
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#define SCR_SEL_TBL_ATN 0x43000000
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struct scr_tblsel {
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u_char sel_0;
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u_char sel_sxfer;
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u_char sel_id;
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u_char sel_scntl3;
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};
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#define SCR_JMP_REL 0x04000000
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#define SCR_ID(id) (((u_long)(id)) << 16)
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/*-----------------------------------------------------------
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**
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** Waiting for Disconnect or Reselect
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**
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**-----------------------------------------------------------
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**
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** WAIT_DISC
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** dummy: <<alternate_address>>
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**
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** WAIT_RESEL
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** <<alternate_address>>
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**
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**-----------------------------------------------------------
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*/
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#define SCR_WAIT_DISC 0x48000000
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#define SCR_WAIT_RESEL 0x50000000
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/*-----------------------------------------------------------
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**
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** Bit Set / Reset
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**
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**-----------------------------------------------------------
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**
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** SET (flags {|.. })
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**
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** CLR (flags {|.. })
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**
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**-----------------------------------------------------------
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*/
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#define SCR_SET(f) (0x58000000 | (f))
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#define SCR_CLR(f) (0x60000000 | (f))
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#define SCR_CARRY 0x00000400
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#define SCR_TRG 0x00000200
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#define SCR_ACK 0x00000040
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#define SCR_ATN 0x00000008
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/*-----------------------------------------------------------
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**
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** Memory to memory move
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**
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**-----------------------------------------------------------
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**
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** COPY (bytecount)
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** << source_address >>
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** << destination_address >>
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**
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**-----------------------------------------------------------
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*/
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#define SCR_COPY(n) (0xc0000000 | (n))
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/*-----------------------------------------------------------
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**
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** Register move and binary operations
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**
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**-----------------------------------------------------------
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**
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** SFBR_REG (reg, op, data) reg = SFBR op data
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** << 0 >>
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**
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** REG_SFBR (reg, op, data) SFBR = reg op data
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** << 0 >>
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**
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** REG_REG (reg, op, data) reg = reg op data
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** << 0 >>
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**
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**-----------------------------------------------------------
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*/
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#define SCR_SFBR_REG(reg,op,data) \
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(0x68000000 | (REG(reg) << 16ul) | (op) | ((data)<<8ul))
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#define SCR_REG_SFBR(reg,op,data) \
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(0x70000000 | (REG(reg) << 16ul) | (op) | ((data)<<8ul))
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#define SCR_REG_REG(reg,op,data) \
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(0x78000000 | (REG(reg) << 16ul) | (op) | ((data)<<8ul))
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#define SCR_LOAD 0x00000000
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#define SCR_SHL 0x01000000
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#define SCR_OR 0x02000000
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#define SCR_XOR 0x03000000
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#define SCR_AND 0x04000000
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#define SCR_SHR 0x05000000
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#define SCR_ADD 0x06000000
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#define SCR_ADDC 0x07000000
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/*-----------------------------------------------------------
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**
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** FROM_REG (reg) reg = SFBR
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** << 0 >>
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**
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** TO_REG (reg) SFBR = reg
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** << 0 >>
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**
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** LOAD_REG (reg, data) reg = <data>
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** << 0 >>
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**
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** LOAD_SFBR(data) SFBR = <data>
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** << 0 >>
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**
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**-----------------------------------------------------------
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*/
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#define SCR_FROM_REG(reg) \
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SCR_REG_SFBR(reg,SCR_OR,0)
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#define SCR_TO_REG(reg) \
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SCR_SFBR_REG(reg,SCR_OR,0)
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#define SCR_LOAD_REG(reg,data) \
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SCR_REG_REG(reg,SCR_LOAD,data)
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#define SCR_LOAD_SFBR(data) \
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(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
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/*-----------------------------------------------------------
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**
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** Waiting for Disconnect or Reselect
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**
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**-----------------------------------------------------------
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**
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** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
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** <<address>>
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**
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** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
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** <<distance>>
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**
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** CALL [ | IFTRUE/IFFALSE ( ... ) ]
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** <<address>>
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**
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** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
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** <<distance>>
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**
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** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
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** <<dummy>>
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**
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** INT [ | IFTRUE/IFFALSE ( ... ) ]
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** <<ident>>
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**
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** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
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** <<ident>>
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**
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** Conditions:
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** WHEN (phase)
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** IF (phase)
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** CARRY
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** DATA (data, mask)
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**
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**-----------------------------------------------------------
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*/
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#define SCR_JUMP 0x80080000
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#define SCR_JUMPR 0x80880000
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#define SCR_CALL 0x88080000
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#define SCR_CALLR 0x88880000
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#define SCR_RETURN 0x90080000
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#define SCR_INT 0x98080000
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#define SCR_INT_FLY 0x98180000
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#define IFFALSE(arg) (0x00080000 | (arg))
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#define IFTRUE(arg) (0x00000000 | (arg))
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#define WHEN(phase) (0x00030000 | (phase))
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#define IF(phase) (0x00020000 | (phase))
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#define DATA(D) (0x00040000 | ((D) & 0xff))
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#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
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#define CARRYSET (0x00200000)
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/*-----------------------------------------------------------
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**
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** SCSI constants.
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**
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**-----------------------------------------------------------
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*/
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/*
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** Messages
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*/
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#define M_COMPLETE (0x00)
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#define M_EXTENDED (0x01)
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#define M_SAVE_DP (0x02)
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#define M_RESTORE_DP (0x03)
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#define M_DISCONNECT (0x04)
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#define M_ID_ERROR (0x05)
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#define M_ABORT (0x06)
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||
#define M_REJECT (0x07)
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#define M_NOOP (0x08)
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||
#define M_PARITY (0x09)
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||
#define M_LCOMPLETE (0x0a)
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||
#define M_FCOMPLETE (0x0b)
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||
#define M_RESET (0x0c)
|
||
#define M_ABORT_TAG (0x0d)
|
||
#define M_CLEAR_QUEUE (0x0e)
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||
#define M_INIT_REC (0x0f)
|
||
#define M_REL_REC (0x10)
|
||
#define M_TERMINATE (0x11)
|
||
#define M_SIMPLE_TAG (0x20)
|
||
#define M_HEAD_TAG (0x21)
|
||
#define M_ORDERED_TAG (0x22)
|
||
#define M_IDENTIFY (0x80)
|
||
|
||
#define M_X_SDTR (0x01)
|
||
|
||
/*
|
||
** Status
|
||
*/
|
||
|
||
#define S_GOOD (0x00)
|
||
#define S_CHECK_COND (0x02)
|
||
#define S_COND_MET (0x04)
|
||
#define S_BUSY (0x08)
|
||
#define S_INT (0x10)
|
||
#define S_INT_COND_MET (0x14)
|
||
#define S_CONFLICT (0x18)
|
||
#define S_TERMINATED (0x20)
|
||
#define S_QUEUE_FULL (0x28)
|
||
#define S_ILLEGAL (0xff)
|
||
|
||
#endif /*__NCR_REG_H__*/
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