f23d3bb7be
CPUs are now configured on mainbus only in dom0, and only to know about their APIC id. virtual CPUs are attached to hypervisor as: vcpu* at hypervisor? and this is what's used as curcpu(). The kernel config files needs to be updated for this, see XEN3_DOM0 or XEN3_DOMU for examples. XEN3_DOM0 now has acpi, MPBIOS and ioapic by default. Note that a Xen dom0 kernel doens't have access to the lapic.
302 lines
7.6 KiB
C
302 lines
7.6 KiB
C
/* $NetBSD: intr.h,v 1.12 2006/09/28 18:53:15 bouyer Exp $ */
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/* NetBSD intr.h,v 1.15 2004/10/31 10:39:34 yamt Exp */
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/*-
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* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum, and by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _XEN_INTR_H_
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#define _XEN_INTR_H_
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#include <machine/intrdefs.h>
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#ifndef _LOCORE
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#include <machine/cpu.h>
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#include <machine/pic.h>
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#include "opt_xen.h"
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/*
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* Struct describing an event channel.
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*/
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struct evtsource {
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int ev_maxlevel; /* max. IPL for this source */
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u_int32_t ev_imask; /* interrupt mask */
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struct intrhand *ev_handlers; /* handler chain */
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struct evcnt ev_evcnt; /* interrupt counter */
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char ev_evname[32]; /* event counter name */
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};
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/*
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* Structure describing an interrupt level. struct cpu_info has an array of
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* IPL_MAX of theses. The index in the array is equal to the stub number of
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* the stubcode as present in vector.s
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*/
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struct intrstub {
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#if 0
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void *ist_entry;
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#endif
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void *ist_recurse;
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void *ist_resume;
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};
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#ifdef XEN3
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/* for x86 compatibility */
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extern struct intrstub i8259_stubs[];
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extern struct intrstub ioapic_edge_stubs[];
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extern struct intrstub ioapic_level_stubs[];
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#endif
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struct iplsource {
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struct intrhand *ipl_handlers; /* handler chain */
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void *ipl_recurse; /* entry for spllower */
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void *ipl_resume; /* entry for doreti */
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u_int32_t ipl_evt_mask1; /* pending events for this IPL */
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u_int32_t ipl_evt_mask2[NR_EVENT_CHANNELS];
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};
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/*
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* Interrupt handler chains. These are linked in both the evtsource and
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* the iplsource.
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* The handler is called with its (single) argument.
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*/
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struct intrhand {
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int (*ih_fun)(void *);
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void *ih_arg;
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int ih_level;
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struct intrhand *ih_ipl_next;
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struct intrhand *ih_evt_next;
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struct cpu_info *ih_cpu;
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};
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struct xen_intr_handle {
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int pirq; /* also contains the APIC_INT_* flags if NIOAPIC > 0 */
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int evtch;
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};
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extern struct intrstub xenev_stubs[];
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#define IUNMASK(ci,level) (ci)->ci_iunmask[(level)]
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extern void Xspllower(int);
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static __inline int splraise(int);
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static __inline void spllower(int);
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static __inline void softintr(int);
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/*
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* Add a mask to cpl, and return the old value of cpl.
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*/
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static __inline int
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splraise(int nlevel)
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{
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int olevel;
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struct cpu_info *ci = curcpu();
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olevel = ci->ci_ilevel;
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if (nlevel > olevel)
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ci->ci_ilevel = nlevel;
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__insn_barrier();
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return (olevel);
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}
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/*
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* Restore a value to cpl (unmasking interrupts). If any unmasked
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* interrupts are pending, call Xspllower() to process them.
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*/
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static __inline void
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spllower(int nlevel)
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{
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struct cpu_info *ci = curcpu();
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u_int32_t imask;
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u_long psl;
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__insn_barrier();
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imask = IUNMASK(ci, nlevel);
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psl = read_psl();
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disable_intr();
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if (ci->ci_ipending & imask) {
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Xspllower(nlevel);
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/* Xspllower does enable_intr() */
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} else {
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ci->ci_ilevel = nlevel;
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write_psl(psl);
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}
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}
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#define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x))
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/*
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* Software interrupt masks
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*
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* NOTE: spllowersoftclock() is used by hardclock() to lower the priority from
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* clock to softclock before it calls softclock().
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*/
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#define spllowersoftclock() spllower(IPL_SOFTCLOCK)
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#define splsoftxenevt() splraise(IPL_SOFTXENEVT)
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/*
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* Miscellaneous
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*/
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#define spl0() spllower(IPL_NONE)
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#define splraiseipl(x) splraise(x)
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#define splx(x) spllower(x)
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#include <sys/spl.h>
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/*
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* Software interrupt registration
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*
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* We hand-code this to ensure that it's atomic.
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*
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* XXX always scheduled on the current CPU.
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*/
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static __inline void
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softintr(int sir)
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{
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struct cpu_info *ci = curcpu();
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__asm volatile("lock ; orl %1, %0" :
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"=m"(ci->ci_ipending) : "ir" (1 << sir));
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}
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/*
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* XXX
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*/
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#define setsoftnet() softintr(SIR_NET)
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/*
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* Stub declarations.
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*/
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extern void Xsoftclock(void);
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extern void Xsoftnet(void);
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extern void Xsoftserial(void);
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extern void Xsoftxenevt(void);
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struct cpu_info;
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extern char idt_allocmap[];
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struct pcibus_attach_args;
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void intr_default_setup(void);
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int x86_nmi(void);
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void intr_calculatemasks(struct evtsource *);
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void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *);
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void intr_disestablish(struct intrhand *);
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const char *intr_string(int);
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void cpu_intr_init(struct cpu_info *);
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int xen_intr_map(int *, int);
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#ifdef INTRDEBUG
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void intr_printconfig(void);
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#endif
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int intr_find_mpmapping(int, int, struct xen_intr_handle *);
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struct pic *intr_findpic(int);
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void intr_add_pcibus(struct pcibus_attach_args *);
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#endif /* !_LOCORE */
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/*
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* Generic software interrupt support.
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*/
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#define X86_SOFTINTR_SOFTCLOCK 0
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#define X86_SOFTINTR_SOFTNET 1
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#define X86_SOFTINTR_SOFTSERIAL 2
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#define X86_NSOFTINTR 3
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#ifndef _LOCORE
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#include <sys/queue.h>
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struct x86_soft_intrhand {
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TAILQ_ENTRY(x86_soft_intrhand)
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sih_q;
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struct x86_soft_intr *sih_intrhead;
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void (*sih_fn)(void *);
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void *sih_arg;
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int sih_pending;
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};
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struct x86_soft_intr {
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TAILQ_HEAD(, x86_soft_intrhand)
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softintr_q;
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int softintr_ssir;
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struct simplelock softintr_slock;
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};
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#define x86_softintr_lock(si, s) \
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do { \
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(s) = splhigh(); \
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simple_lock(&si->softintr_slock); \
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} while (/*CONSTCOND*/ 0)
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#define x86_softintr_unlock(si, s) \
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do { \
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simple_unlock(&si->softintr_slock); \
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splx((s)); \
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} while (/*CONSTCOND*/ 0)
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void *softintr_establish(int, void (*)(void *), void *);
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void softintr_disestablish(void *);
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void softintr_init(void);
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void softintr_dispatch(int);
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#define softintr_schedule(arg) \
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do { \
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struct x86_soft_intrhand *__sih = (arg); \
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struct x86_soft_intr *__si = __sih->sih_intrhead; \
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int __s; \
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\
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x86_softintr_lock(__si, __s); \
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if (__sih->sih_pending == 0) { \
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TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \
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__sih->sih_pending = 1; \
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softintr(__si->softintr_ssir); \
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} \
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x86_softintr_unlock(__si, __s); \
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} while (/*CONSTCOND*/ 0)
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#endif /* _LOCORE */
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#endif /* _XEN_INTR_H_ */
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